From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AF883043D4; Sat, 25 Oct 2025 16:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761408955; cv=none; b=Zy9ZNpj3cz9BUUVbLiepE199idgKx9b2QR9BN5eyIkUJa/NmUgNahKIlwWEDpAql5hcf9Ak2pcKs2r38/YfB2Lw0UaV/OebdFuEMMGc/VUHQCulQKtxJMuYxlo8+FuPxJwmXMw+kMGO29/a8MhQAZxtQixVpcJG9gSNZPg9zHMM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761408955; c=relaxed/simple; bh=i3A51i6kEV+oroiLNKRB/JhjhBRzQv0vm4A/QpygqoM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lwMgvagbnOLzrb8+ec0R336RAYTQ65MsQFPiFomQGVDMVYiOc5e4f/6wJtH683qi/s6Ab4fdlH5euExATG2aeCqqSmuiO+hd0lQpdUCLOEmhc6MMGbmn7CrtSwBo2rBNy27T61zgve8gLhmGN/YS5YKKrDM+JbholY3lBFNptNE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L8IbOn+a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L8IbOn+a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D5A1C116B1; Sat, 25 Oct 2025 16:15:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761408954; bh=i3A51i6kEV+oroiLNKRB/JhjhBRzQv0vm4A/QpygqoM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L8IbOn+aH6aLHtOVBl/Yerqzvg6gxnStEErBC/REawh+62QH6Sy05OCsFKnGTSkSL zUkC5bHF2Kxp6AoPX2HFgenWRQ3G0ntP7SW1vqfPapp9O62tADH3FrSKzZMzYV1lW7 Cz+RuafGLX0xKXDAy15bVBRNyWFmMKS0d3iiFtMAIZVxr1F4TKNkKq86FJYFjcaUol yJ0xRlNL3BX1PaWE6AkpDMwICGke5QMVsR2W55DFCK/WhLmfuT9MmeTigbmA72oLd3 Way1M0zafTT7NZNVo8Ry/Xf24MeIqHqUxQc6J4kS8wtIxBbNJIBKtNu5klR/KGU7Kb 72BDkaBylSZ+A== From: Sasha Levin To: patches@lists.linux.dev, stable@vger.kernel.org Cc: Marcos Del Sol Vives , Bjorn Helgaas , Sasha Levin , linux-pci@vger.kernel.org Subject: [PATCH AUTOSEL 6.17-5.4] PCI: Disable MSI on RDC PCI to PCIe bridges Date: Sat, 25 Oct 2025 11:56:20 -0400 Message-ID: <20251025160905.3857885-149-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251025160905.3857885-1-sashal@kernel.org> References: <20251025160905.3857885-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.17.5 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Marcos Del Sol Vives [ Upstream commit ebc7086b39e5e4f3d3ca82caaea20538c9b62d42 ] RDC PCI to PCIe bridges, present on Vortex86DX3 and Vortex86EX2 SoCs, do not support MSIs. If enabled, interrupts generated by PCIe devices never reach the processor. I have contacted the manufacturer (DM&P) and they confirmed that PCI MSIs need to be disabled for them. Signed-off-by: Marcos Del Sol Vives Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20250705233209.721507-1-marcos@orca.pet Signed-off-by: Sasha Levin --- LLM Generated explanations, may be completely bogus: YES Reasons this is a good stable backport candidate - Fixes a real hardware bug: The commit message states RDC PCI→PCIe bridges “do not support MSIs” and that when enabled, “interrupts generated by PCIe devices never reach the processor.” That is a functional breakage for devices behind these bridges, not a feature change. - Minimal, targeted change: The patch adds a single quirk line to disable MSI only behind the affected bridge: - Adds: DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); in drivers/pci/quirks.c next to other vendor-specific MSI-disable quirks such as AMD/VIA/ATI (drivers/pci/quirks.c:2717-2719). - The quirk uses existing helper quirk_disable_msi() (drivers/pci/quirks.c:2710), which only sets a flag on the subordinate bus if the device is a bridge: - Sets bus flag: dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; - The function is compiled under CONFIG_PCI_MSI (drivers/pci/quirks.c:2686), so it is inert if MSI is not enabled. - Correct mechanism and stage: - Bus-level gating is the standard way to suppress MSI/MSI-X behind a broken bridge. The MSI core checks this flag up the bus hierarchy and refuses to enable MSI/MSI-X when set (drivers/pci/msi/msi.c:62). - The flag used is the canonical one (include/linux/pci.h:259), and the vendor macro is already present (include/linux/pci_ids.h:2412). - Uses DECLARE_PCI_FIXUP_FINAL(), consistent with other similar quirks (drivers/pci/quirks.c:2717-2719), so it runs late enough to have a subordinate bus to mark and before drivers enable MSI. - Scope-limited and precedent: - Only affects devices with vendor RDC and device ID 0x1031, and only if they are bridges (quirk_disable_msi() early-exits otherwise; drivers/pci/quirks.c:2712). - Mirrors long-standing patterns for known-broken bridges (e.g., AMD 8131, VIA, ATI entries at drivers/pci/quirks.c:2717-2719). - Risk assessment: - Primary effect is that devices behind the affected bridge will use INTx instead of MSI/MSI-X. That may reduce performance but restores correctness (avoids lost interrupts). If a device strictly requires MSI/MSI-X, it could not have worked reliably on this hardware anyway, so the quirk does not introduce a new regression in practice. - No architectural changes, no API changes, no cross-subsystem impact; single-file quirk addition under an existing guard. - Stable policy fit: - Hardware workarounds that fix real user-visible bugs are routinely backported. - The change is small, well-scoped, and follows existing patterns. - While there is no explicit “Cc: stable” in the provided message, this class of PCI quirks is commonly accepted for stable. Conclusion - Backport Status: YES. This one-line quirk reliably prevents MSI/MSI-X enablement behind RDC bridges known to drop MSI interrupts, restoring device functionality with minimal risk. drivers/pci/quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d97335a401930..6eb3d20386e95 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2717,6 +2717,7 @@ static void quirk_disable_msi(struct pci_dev *dev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); /* * The APC bridge device in AMD 780 family northbridges has some random -- 2.51.0