[PATCH AUTOSEL 6.17-5.15] rtc: pcf2127: clear minute/second interrupt

[Sasha Levin <sashal@kernel.org>]

From: Josua Mayer <josua@solid-run.com>

[ Upstream commit a6f1a4f05970664004a9370459c6799c1b2f2dcf ]

PCF2127 can generate interrupt every full second or minute configured
from control and status register 1, bits MI (1) and SI (0).

On interrupt control register 2 bit MSF (7) is set and must be cleared
to continue normal operation.

While the driver never enables this interrupt on its own, users or
firmware may do so - e.g. as an easy way to test the interrupt.

Add preprocessor definition for MSF bit and include it in the irq
bitmask to ensure minute and second interrupts are cleared when fired.

This fixes an issue where the rtc enters a test mode and becomes
unresponsive after a second interrupt has fired and is not cleared in
time. In this state register writes to control registers have no
effect and the interrupt line is kept asserted [1]:

[1] userspace commands to put rtc into unresponsive state:
$ i2cget -f -y 2 0x51 0x00
0x04
$ i2cset -f -y 2 0x51 0x00 0x05 # set bit 0 SI
$ i2cget -f -y 2 0x51 0x00
0x84 # bit 8 EXT_TEST set
$ i2cset -f -y 2 0x51 0x00 0x05 # try overwrite control register
$ i2cget -f -y 2 0x51 0x00
0x84 # no change

Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Bruno Thomsen <bruno.thomsen@gmail.com>
Link: https://lore.kernel.org/r/20250825-rtc-irq-v1-1-0133319406a7@solid-run.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

YES
Clearing the PCF2127 minute/second status flag in the IRQ handler
prevents the controller from locking into EXT_TEST mode when firmware or
userspace enable MI/SI for basic interrupt testing. The patch simply
defines the missing MSF bit and adds it to the mask we already use when
acknowledging CTRL2 status flags, so the interrupt line is released and
register writes start working again.

- `drivers/rtc/rtc-pcf2127.c:45` now names `PCF2127_BIT_CTRL2_MSF`, the
  documented status bit that latches when MI/SI fire; before this change
  the driver never referenced it and therefore never cleared it.
- Including the new bit in `PCF2127_CTRL2_IRQ_MASK` (`drivers/rtc/rtc-
  pcf2127.c:97-101`) ensures the IRQ acknowledge path clears MSF
  alongside AF/WDTF/TSF2. With the old mask, once the second interrupt
  hit the device stayed in test mode and ignored control-register
  writes, exactly as reproduced in the commit message.
- The actual clearing happens in the existing handler (`drivers/rtc/rtc-
  pcf2127.c:792-794`), so no new logic is introduced—only the correct
  bit is now masked off. PCF2131 handling remains untouched, so the
  change is tightly scoped to the affected variants.
- This is a real user-visible hang (persistent interrupt line, inability
  to reconfigure the RTC) triggered by a plausible configuration, while
  the fix is minimal and mirrors how the PCF2123 driver already clears
  its MSF flag (`drivers/rtc/rtc-pcf2123.c:70-78`), keeping regression
  risk low.

Given the clear failure mode and the tiny, well-contained fix, this is
an excellent candidate for stable backporting.

 drivers/rtc/rtc-pcf2127.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 2e1ac0c42e932..3ba1de30e89c2 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -42,6 +42,7 @@
 #define PCF2127_BIT_CTRL2_AF			BIT(4)
 #define PCF2127_BIT_CTRL2_TSF2			BIT(5)
 #define PCF2127_BIT_CTRL2_WDTF			BIT(6)
+#define PCF2127_BIT_CTRL2_MSF			BIT(7)
 /* Control register 3 */
 #define PCF2127_REG_CTRL3		0x02
 #define PCF2127_BIT_CTRL3_BLIE			BIT(0)
@@ -96,7 +97,8 @@
 #define PCF2127_CTRL2_IRQ_MASK ( \
 		PCF2127_BIT_CTRL2_AF | \
 		PCF2127_BIT_CTRL2_WDTF | \
-		PCF2127_BIT_CTRL2_TSF2)
+		PCF2127_BIT_CTRL2_TSF2 | \
+		PCF2127_BIT_CTRL2_MSF)
 
 #define PCF2127_MAX_TS_SUPPORTED	4
 
-- 
2.51.0