From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7D6E1F7586; Mon, 27 Oct 2025 19:07:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761592055; cv=none; b=G7375ZpZmjCgCl5LUhxB0Vsznh8t8ER10AQT4vDrxZp4g8RMMdkgYtY6OLBo096nlxNTJeRjtP72oId/t+F+hVkD/PKyIkUr+PWo51SU9Wjaw8HaVmnWlv2JqGVmXkG3AjPp+UarIDyKNTmX0L6YjuUhGvFOdE7mtVu7oIjtTWo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761592055; c=relaxed/simple; bh=rSPMSW5YHRiLHV1Nk64hhKuRLdxf3d/2VNCK0c84LMk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gZz/1Cl/TO/JNw9wZ/nVb5juAlPu0lYtLmgbhngIaWe4Bjopf3w1620GqUrPwyiGFezbW/gRx0w1V83kTWxEwmSZTNZmuaQQJPligQn1UjSiOhEHqcvOYaTNfkVfauwRaYaRSTIO1aQZAGLTJthNkLOOMOUIQF+BrFS/7p6nfGo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=ZbBbZmGH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="ZbBbZmGH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4143C4CEFD; Mon, 27 Oct 2025 19:07:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1761592055; bh=rSPMSW5YHRiLHV1Nk64hhKuRLdxf3d/2VNCK0c84LMk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZbBbZmGHYB3iz1pLTLomV/SiOISsmvwpL+kgXGaQDdfawTzysfADwDh7trcawEdXl t+PY4QzziDukPxs9RJXhmPaXTI5gdIdJxvB70mxWKtA8AH57ANPlhtTxCQ1p66CaW4 lybgmK382lDmkzSTqvXUAUK5HtOM5Dxc5vuehxb0= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Anup Patel , Heiko Stuebner , Tsukasa OI , Atish Patra , Palmer Dabbelt , Sasha Levin Subject: [PATCH 5.15 071/123] RISC-V: Correctly print supported extensions Date: Mon, 27 Oct 2025 19:35:51 +0100 Message-ID: <20251027183448.298768724@linuxfoundation.org> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251027183446.381986645@linuxfoundation.org> References: <20251027183446.381986645@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Tsukasa OI [ Upstream commit 58004f266918912771ee71f46bfb92bf64ab9108 ] This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel Tested-by: Heiko Stuebner Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra Signed-off-by: Palmer Dabbelt Stable-dep-of: d2721bb165b3 ("RISC-V: Don't print details of CPUs disabled in DT") Signed-off-by: Sasha Levin --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d6..dd3d57eb4eead 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); -- 2.51.0