From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79F6532143D; Mon, 27 Oct 2025 18:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761591348; cv=none; b=NJqiD0vjTjbSpacQ/Fha9ZPGUHfIRcVfEp02RWxV/f+QjNDAbmlcqqkaLTV5Iupd+wNCGcTnQ/rGrffOqvxHIxvyO1g8oSQ2zDZ7iCC7fiX3FY46WZU1RklwqDHChNXAh6mzD+w+C1g8y4LTbidq2sVMkYfuycnXRorM0fYqhog= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761591348; c=relaxed/simple; bh=+6IUmWzwCsizl+ibnB/3RSBPlJWeRaEAAQuCwRL/zu0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eJjfUoYCdekhEYvXg0/RYMSPJM+xT0O2a1aDLxTz5NQFY3DQ7U2264r7d5JOw4SVVoU7CteqA7I9woOUahk4myzj+XLsaIDFBFc4aw5KFiIrMb3mbMWzbhUHZXGcxF3R1axPyTbMg6Y3a5TiUlUEEglgk7WzV6a0bpcaOre0+Is= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=xrRe5TBz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="xrRe5TBz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DB34C4CEF1; Mon, 27 Oct 2025 18:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1761591348; bh=+6IUmWzwCsizl+ibnB/3RSBPlJWeRaEAAQuCwRL/zu0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xrRe5TBzSyykqlj/Xw4FiQkhRmxQKq2cLKCIu0DmwjEVSeE7VuV3rGLTg+iYxUpc2 Z1dnYik6kPbO228YBxWNkcPJWP2pXJzesthvydnqjamty62QbHgGvc/vwKKpB2bokW 7L86rk4J67ancFCDILkFvhCHHRX74f6LSlwuhCl8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Pratyush Yadav , Santhosh Kumar K , Mark Brown Subject: [PATCH 5.10 163/332] spi: cadence-quadspi: Flush posted register writes before INDAC access Date: Mon, 27 Oct 2025 19:33:36 +0100 Message-ID: <20251027183528.931599299@linuxfoundation.org> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251027183524.611456697@linuxfoundation.org> References: <20251027183524.611456697@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Pratyush Yadav commit 29e0b471ccbd674d20d4bbddea1a51e7105212c5 upstream. cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K Message-ID: <20250905185958.3575037-2-s-k6@ti.com> Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-cadence-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -502,6 +502,7 @@ static int cqspi_indirect_read_execute(s reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); + readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ while (remaining > 0) { if (!wait_for_completion_timeout(&cqspi->transfer_complete, @@ -611,6 +612,8 @@ static int cqspi_indirect_write_execute( reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ + /* * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access * Controller programming sequence, couple of cycles of