From: Bjorn Helgaas <helgaas@kernel.org>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: joro@8bytes.org, rafael@kernel.org, bhelgaas@google.com,
alex@shazbot.org, jgg@nvidia.com, kevin.tian@intel.com,
will@kernel.org, robin.murphy@arm.com, lenb@kernel.org,
baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
kvm@vger.kernel.org, patches@lists.linux.dev,
pjaroszynski@nvidia.com, vsethi@nvidia.com, etzhao1900@gmail.com
Subject: Re: [PATCH v5 4/5] iommu: Introduce iommu_dev_reset_prepare() and iommu_dev_reset_done()
Date: Mon, 17 Nov 2025 17:04:14 -0600 [thread overview]
Message-ID: <20251117230414.GA2537490@bhelgaas> (raw)
In-Reply-To: <28af027371a981a2b4154633e12cdb1e5a11da4a.1762835355.git.nicolinc@nvidia.com>
On Mon, Nov 10, 2025 at 09:12:54PM -0800, Nicolin Chen wrote:
> PCIe permits a device to ignore ATS invalidation TLPs, while processing a
> reset. This creates a problem visible to the OS where an ATS invalidation
> command will time out. E.g. an SVA domain will have no coordination with a
> reset event and can racily issue ATS invalidations to a resetting device.
s/TLPs, while/TLPs while/
> The OS should do something to mitigate this as we do not want production
> systems to be reporting critical ATS failures, especially in a hypervisor
> environment. Broadly, OS could arrange to ignore the timeouts, block page
> table mutations to prevent invalidations, or disable and block ATS.
>
> The PCIe spec in sec 10.3.1 IMPLEMENTATION NOTE recommends to disable and
> block ATS before initiating a Function Level Reset. It also mentions that
> other reset methods could have the same vulnerability as well.
>
> Provide a callback from the PCI subsystem that will enclose the reset and
> have the iommu core temporarily change all the attached domain to BLOCKED.
> After attaching a BLOCKED domain, IOMMU hardware would fence any incoming
> ATS queries. And IOMMU drivers should also synchronously stop issuing new
> ATS invalidations and wait for all ATS invalidations to complete. This can
> avoid any ATS invaliation timeouts.
>
> However, if there is a domain attachment/replacement happening during an
> ongoing reset, ATS routines may be re-activated between the two function
> calls. So, introduce a new resetting_domain in the iommu_group structure
> to reject any concurrent attach_dev/set_dev_pasid call during a reset for
> a concern of compatibility failure. Since this changes the behavior of an
> attach operation, update the uAPI accordingly.
>
> Note that there are two corner cases:
> 1. Devices in the same iommu_group
> Since an attachment is always per iommu_group, disallowing one device
> to switch domains (or HWPTs in iommufd) would have to disallow others
> in the same iommu_group to switch domains as well. So, play safe by
> preventing a shared iommu_group from going through the iommu reset.
> 2. SRIOV devices that its PF is resetting while its VF isn't
Slightly awkward. Maybe:
2. An SR-IOV PF that is being reset while its VF is not
(Obviously resetting a PF destroys all the VFs, which I guess is what
you're hinting at below.)
> In such case, the VF itself is already broken. So, there is no point
> in preventing PF from going through the iommu reset.
> + * iommu_dev_reset_prepare() - Block IOMMU to prepare for a device reset
> + * @dev: device that is going to enter a reset routine
> + *
> + * When certain device is entering a reset routine, it wants to block any IOMMU
> + * activity during the reset routine. This includes blocking any translation as
> + * well as cache invalidation (especially the device cache).
> + *
> + * This function attaches all RID/PASID of the device's to IOMMU_DOMAIN_BLOCKED
> + * allowing any blocked-domain-supporting IOMMU driver to pause translation and
> + * cahce invalidation, but leaves the software domain pointers intact so later
s/cahce/cache/
next prev parent reply other threads:[~2025-11-17 23:04 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 5:12 [PATCH v5 0/5] Disable ATS via iommu during PCI resets Nicolin Chen
2025-11-11 5:12 ` [PATCH v5 1/5] iommu: Lock group->mutex in iommu_deferred_attach() Nicolin Chen
2025-11-12 2:47 ` Baolu Lu
2025-11-11 5:12 ` [PATCH v5 2/5] iommu: Tiny domain for iommu_setup_dma_ops() Nicolin Chen
2025-11-12 5:22 ` Baolu Lu
2025-11-14 9:17 ` Tian, Kevin
2025-11-14 9:18 ` Tian, Kevin
2025-11-11 5:12 ` [PATCH v5 3/5] iommu: Add iommu_driver_get_domain_for_dev() helper Nicolin Chen
2025-11-12 5:58 ` Baolu Lu
2025-11-12 17:41 ` Nicolin Chen
2025-11-18 7:02 ` Nicolin Chen
2025-11-19 2:47 ` Baolu Lu
2025-11-19 2:57 ` Nicolin Chen
2025-11-12 8:52 ` kernel test robot
2025-11-14 9:18 ` Tian, Kevin
2025-11-11 5:12 ` [PATCH v5 4/5] iommu: Introduce iommu_dev_reset_prepare() and iommu_dev_reset_done() Nicolin Chen
2025-11-12 6:18 ` Baolu Lu
2025-11-12 17:43 ` Nicolin Chen
2025-11-14 9:37 ` Tian, Kevin
2025-11-14 18:26 ` Nicolin Chen
2025-11-17 4:59 ` Tian, Kevin
2025-11-17 19:27 ` Nicolin Chen
2025-11-17 23:04 ` Bjorn Helgaas [this message]
2025-11-11 5:12 ` [PATCH v5 5/5] pci: Suspend iommu function prior to resetting a device Nicolin Chen
2025-11-14 9:45 ` Tian, Kevin
2025-11-14 18:00 ` Nicolin Chen
2025-11-17 4:52 ` Tian, Kevin
2025-11-17 19:26 ` Nicolin Chen
2025-11-18 0:29 ` Tian, Kevin
2025-11-18 1:42 ` Nicolin Chen
2025-11-18 5:38 ` Baolu Lu
2025-11-18 6:53 ` Nicolin Chen
2025-11-18 7:53 ` Tian, Kevin
2025-11-18 8:17 ` Nicolin Chen
2025-11-17 22:58 ` Bjorn Helgaas
2025-11-18 8:16 ` Nicolin Chen
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