[PATCH 6.18 140/175] net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4

Greg Kroah-Hartman
2026-02-09T14:32:50Z

From: Claudiu Manoil <claudiu.manoil@nxp.com>

[ Upstream commit a69c17230cab07bd156f894fdc82bd78b43ea72f ]

For ENETC v4 these settings are controlled by the global ENETC
message and buffer cache attribute registers (EnBCAR and EnMCAR),
from the IERB register block.

The hardcoded cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.

Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Link: https://patch.msgid.link/20260130141035.272471-2-claudiu.manoil@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c
index f410c245ea918..b6e3fb0401619 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc.c
@@ -2503,10 +2503,13 @@ int enetc_configure_si(struct enetc_ndev_priv *priv)
struct enetc_hw *hw = &si->hw;
int err;

- /* set SI cache attributes */
- enetc_wr(hw, ENETC_SICAR0,
- ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
- enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);
+ if (is_enetc_rev1(si)) {
+ /* set SI cache attributes */
+ enetc_wr(hw, ENETC_SICAR0,
+ ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
+ enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);
+ }
+
/* enable SI */
enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN);

--
2.51.0