[PATCH AUTOSEL 6.19-6.12] drm/amd/display: avoid dig reg access timeout on usb4 link training fail

Sasha Levin
2026-02-14T01:03:18Z

From: Zhongwei <Zhongwei.Zhang@amd.com>

[ Upstream commit 15b1d7b77e9836ff4184093163174a1ef28bbdd7 ]

[Why]
When usb4 link training fails, the dpia sym clock will be disabled and SYMCLK
source should be changed back to phy clock. In enable_streams, it is
assumed that link training succeeded and will switch from refclk to
phy clock. But phy clk here might not be on. Dig reg access timeout
will occur.

[How]
When enable_stream is hit, check if link training failed for usb4.
If it did, fall back to the ref clock to avoid reg access timeout.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Zhongwei <Zhongwei.Zhang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

This is widely used across the DC codebase — no dependency concerns.

### 8. SUMMARY

**What it fixes:** A register access timeout that occurs when USB4
(DPIA) link training fails. The timeout happens because the code
unconditionally enables the symclk (which requires phy clock to be
running), but when link training failed, the phy clock is off. This
causes the register access to hang/timeout.

**How it fixes it:** By adding a check that mirrors the existing
128b/132b signal handling — when link training has failed (detected by
LINK_RATE_UNKNOWN, endpoint type is USB4 DPIA, and link is not active),
it disables the symclk instead of enabling it, falling back to the
reference clock. Additionally adds a NULL check on `link_enc`.

**Meets stable criteria:**
- Obviously correct: mirrors existing pattern for 128b/132b, reviewed
and tested by AMD team
- Fixes a real bug: register access timeout causing display failures
- Small and contained: ~15 lines in one function in one file
- No new features: purely defensive error handling
- Low regression risk: only changes behavior in the failure path

**YES** — This is a well-contained bug fix for a real hardware timeout
issue affecting USB4 display connections. It's small, well-reviewed,
well-tested, follows existing patterns in the code, and has very low
regression risk.

**YES**

.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index c8ff8ae85a030..517d4c08d34c4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -3058,9 +3058,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
}
} else {
- if (dccg->funcs->enable_symclk_se)
- dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
+ if (dccg->funcs->enable_symclk_se && link_enc) {
+ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA
+ && link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN
+ && !link->link_status.link_active) {
+ if (dccg->funcs->disable_symclk_se)
+ dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
link_enc->transmitter - TRANSMITTER_UNIPHY_A);
+ } else
+ dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
+ link_enc->transmitter - TRANSMITTER_UNIPHY_A);
+ }
}

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)
--
2.51.0