From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78FC5346AD3 for ; Sat, 28 Feb 2026 18:08:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772302091; cv=none; b=pLZcoDJO8EQUxgzRUZ4jIp9W9BoprVv1sjrChqjGyoPWa+MkekpTtmUFTmRqdhv3OmUDUX6NWd1jDYP4mXXi4olU6kC+CxM9oAJqPXJOef+egNQu2+2PDHvlRUk7+X34Admc+vH5xYhNCMQc1ybvWP/bCrvjoVhZuOERcJG+Wio= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772302091; c=relaxed/simple; bh=6jFmzm5AQ8bbB8HU9/RIjU49jukgVqAKBzTdo+2ra3s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SBTnA+fQzbieZTY6DVnyIncOBaOp4BLwU9xeGLW0ApCyrN1dNzGvqpWPViv65e91121z9q86Xvl02RnUppNQKSxUxSkPN/QEs1erC9ztJZFeyGFEnWETo20lCqtmsvOB3Sovr90xMS0dqpqmRqS3TKFwEZZCMl7Fqoo05OvaF2Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eRN9bPm8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eRN9bPm8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF4B1C19423; Sat, 28 Feb 2026 18:08:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772302091; bh=6jFmzm5AQ8bbB8HU9/RIjU49jukgVqAKBzTdo+2ra3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eRN9bPm8tozLhFTbe2GZEkzJ5AH3RCMk0y2/IJ8ch75fEsfSn4CedcMap2YDhLDUr lz8hlotuxwoTXHx8xMTxaHgeeAVYrwb68CD0g/pwcGKZse71esshIi50tdp9TjAr+u y/ZQ/OQ0UtBgjM6fcH2bhiwu7RThVXiyXVzU5sR8NtkB53unUG0tGDDo5DieDvpsQp cLt7PrswlYNNAvz9x7SV4zBkZh3jAlzNQcOhBYd6U/ObSxm2Bmg9ckbPmPEDfRdgbp Zw/ju+244pOzYsUbJ0e9s2SS4XbLL4iemw+Rr0PXX/6Kq0sAOcc5CwBvhwKAYE0yw1 F3tZGlYDr/tAA== From: Sasha Levin To: patches@lists.linux.dev Cc: Jerome Brunet , Neil Armstrong , Sasha Levin Subject: [PATCH 6.6 075/283] arm64: dts: amlogic: gx: assign the MMC signal clocks Date: Sat, 28 Feb 2026 13:03:37 -0500 Message-ID: <20260228180709.1583486-75-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228180709.1583486-1-sashal@kernel.org> References: <20260228180709.1583486-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Jerome Brunet [ Upstream commit 406706559046eebc09a31e8ae5e78620bfd746fe ] The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clocks to make sure they are properly configured Fixes: 50662499f911 ("ARM64: dts: meson-gx: Use correct mmc clock source 0") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-4-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index ed00e67e6923a..851ae89dd17fa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -799,6 +799,9 @@ &sd_emmc_a { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -807,6 +810,9 @@ &sd_emmc_b { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -815,6 +821,9 @@ &sd_emmc_c { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index f58d1790de1cb..f7fafebafd809 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -869,6 +869,9 @@ &sd_emmc_a { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -877,6 +880,9 @@ &sd_emmc_b { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -885,6 +891,9 @@ &sd_emmc_c { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { -- 2.51.0