From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E6ED2737F2 for ; Sat, 28 Feb 2026 18:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772302345; cv=none; b=MmcJLHowF0AGwvekVw4QJlOXkLICZqqQ/9Q/kRa0xq3RzpcezX7xjKFqAEH9AMWyN3JJBpE9OhzB7A5JLQpu2Gs6Cma2fNHppbdOahOWLCycy+K1bc89GwKPIUCA5zVKw9DTvUyNURQcFQ5IWEz9Z85TtS35FB0iDVuu6ZrfbLI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772302345; c=relaxed/simple; bh=O9h42/cOQQiz3I0DYi2IVQ/catvVPOV0PDwNmJp7T+I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bh06/H39RaNUZqdBCP5GQL1WDabR2MTKqY8wHn1O51bo+hNdjS5EEKp718RSii4vvWFoc13+eKlixql1xJOxpzNv2ZBlI24BCm3enJVbTbOF4TBjyRAFofCBqRWzHzmIluT9u52BYwUTAHscdlMh0u6VA8YIPDyL+Vx8tJJoH+w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RGgUjFE3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RGgUjFE3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7FE47C19423; Sat, 28 Feb 2026 18:12:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772302345; bh=O9h42/cOQQiz3I0DYi2IVQ/catvVPOV0PDwNmJp7T+I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RGgUjFE3wf89Bc+H41tAje8b66PUmkVSQyTaIyYn0g5xLiXgqtl/fm8yBHftPwPAs lZXyghziGkxC543lDwWgFctQQBowwBQWOn9RlxV+OcnYKmaispBj69aIy35QZDHnt0 VrhX0DMSRjJZo6ZWMycGFO+z4P9Nstxglf5yxdHycRTpT2g21fUuhUyC2RBAXUdqhH vRc4L9RZeuNNwy6VFIVgzkvGpHknqx4lI3Ac7SLx37cKEbNsNykmPv9M0VAVDnbhF7 oCMZ25MPv9pZaJh3rc4vMZI1q9ba6Tvn+z6od7KSRCOLjPOzRiXXYvQn4iJsv6DDmO 3oti24SAJah0g== From: Sasha Levin To: patches@lists.linux.dev Cc: Jerome Brunet , Neil Armstrong , Sasha Levin Subject: [PATCH 6.1 068/232] arm64: dts: amlogic: gx: assign the MMC signal clocks Date: Sat, 28 Feb 2026 13:08:41 -0500 Message-ID: <20260228181127.1592657-68-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228181127.1592657-1-sashal@kernel.org> References: <20260228181127.1592657-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Jerome Brunet [ Upstream commit 406706559046eebc09a31e8ae5e78620bfd746fe ] The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clocks to make sure they are properly configured Fixes: 50662499f911 ("ARM64: dts: meson-gx: Use correct mmc clock source 0") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-4-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 256c46771db78..c57a6f37bc2af 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -779,6 +779,9 @@ &sd_emmc_a { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -787,6 +790,9 @@ &sd_emmc_b { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -795,6 +801,9 @@ &sd_emmc_c { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index a689bd14ece99..fb6e8c466811f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -848,6 +848,9 @@ &sd_emmc_a { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -856,6 +859,9 @@ &sd_emmc_b { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -864,6 +870,9 @@ &sd_emmc_c { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { -- 2.51.0