From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37D2F35AC01 for ; Sat, 28 Feb 2026 18:18:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772302690; cv=none; b=XlnQKl/TFj2ivMbby9TUwNbGl77CQLMkFZbdv4inT8MtzvywqVPHZoMbHzFQSEq2ma2Df7FZD6j8PP266tqxEJsP6gEYlwG/MtLa2vH/56OBlPGl1fXVULjjaj4f4mO0hRktJjPAtqBAXKKxCyH0HDEENLNs2wKG+sJi1VQCbWE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772302690; c=relaxed/simple; bh=O9h42/cOQQiz3I0DYi2IVQ/catvVPOV0PDwNmJp7T+I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hqRPxFcyCCOlgw1DMfAICKb/2lNL6lJdSRSjgLgvJfjNG82vbBLG1YSV+nJJ7N08mBCkamOy9pkkryh3xOogJAiA7gE+/87BkCLo6hqPHXOO781atNl5WZyGtjO8bhq3oBHveAxFZaWJVK7Zm6XKE1Udeikz4QyIOsNioxpXYzo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eyApfrfO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eyApfrfO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E4E4C19423; Sat, 28 Feb 2026 18:18:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772302690; bh=O9h42/cOQQiz3I0DYi2IVQ/catvVPOV0PDwNmJp7T+I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eyApfrfOis185OfgFrrlOUnqsUxpf58L3a8x0RRbuTPmLCXzBIxszkat9OJWTONuO gvKmXHmBQsUMGpK18bzCRadDo01lwimlz1oarq4m20KuL+F8Am6QxytgR8cpLHLxSy gO8DV2JxhsieaZTVIru6w/Cc6Na8PJSqo4+x2vIroEZDNgMVSdE0CWgEf18gXUVCeo wQJcZQ2m9dOLR+A4yt901rNQLW+s8N+TNKc9hFhHBNP/pFCR5rKeeGAMt/26zXpAqA NBiout12wwEjDv5DRHQHQoDglCybyu/dbbh4wYkXTIQE58hqm0eC4LOSb0sjk8l+ry 0Ud+Nu6Zs047A== From: Sasha Levin To: patches@lists.linux.dev Cc: Jerome Brunet , Neil Armstrong , Sasha Levin Subject: [PATCH 5.10 043/147] arm64: dts: amlogic: gx: assign the MMC signal clocks Date: Sat, 28 Feb 2026 13:15:51 -0500 Message-ID: <20260228181736.1605592-43-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260228181736.1605592-1-sashal@kernel.org> References: <20260228181736.1605592-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Jerome Brunet [ Upstream commit 406706559046eebc09a31e8ae5e78620bfd746fe ] The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clocks to make sure they are properly configured Fixes: 50662499f911 ("ARM64: dts: meson-gx: Use correct mmc clock source 0") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-4-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 256c46771db78..c57a6f37bc2af 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -779,6 +779,9 @@ &sd_emmc_a { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -787,6 +790,9 @@ &sd_emmc_b { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -795,6 +801,9 @@ &sd_emmc_c { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index a689bd14ece99..fb6e8c466811f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -848,6 +848,9 @@ &sd_emmc_a { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -856,6 +859,9 @@ &sd_emmc_b { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -864,6 +870,9 @@ &sd_emmc_c { <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { -- 2.51.0