[PATCH 5.10 035/147] arm64: dts: qcom: sdm630: correct QFPROM byte offsets

Sasha Levin
2026-02-28T18:18:03Z

From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[ Upstream commit 74b0fbd6048f8f4caaed712ceeca52c6034e9ad6 ]

The NVMEM bindings expect that 'bits' property holds offset and size of
region within a byte, so it applies a constraint of <0, 7> for the
offset. Using 25 as HSTX trim offset is within 4-byte QFPROM word, but
outside of the byte:

sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: hstx-trim@240:bits:0:0: 25 is greater than the maximum of 7
sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: gpu-speed-bin@41a0:bits:0:0: 21 is greater than the maximum of 7

Align the offsets to match the bindings.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220505113802.243301-6-krzysztof.kozlowski@linaro.org
Stable-dep-of: e814796dfcae ("arm64: dts: qcom: sdm630: fix gpu_speed_bin size")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index d810ab74204c5..c39e67fa64650 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -462,13 +462,13 @@ qfprom: qfprom@780000 {
#size-cells = <1>;

qusb2_hstx_trim: hstx-trim@240 {
- reg = <0x240 0x1>;
- bits = <25 3>;
+ reg = <0x243 0x1>;
+ bits = <1 3>;
};

gpu_speed_bin: gpu-speed-bin@41a0 {
- reg = <0x41a0 0x1>;
- bits = <21 7>;
+ reg = <0x41a2 0x1>;
+ bits = <5 7>;
};
};

--
2.51.0