Re: [PATCH] iommu/dma: Always allow DMA-FQ when iommupt provides the iommu_domain

[Jason Gunthorpe <jgg@nvidia.com>]

On Wed, Apr 01, 2026 at 01:53:05PM +0100, Robin Murphy wrote:
> On 2026-03-26 7:30 pm, Jason Gunthorpe wrote:
> > iommupt always supports the semantics required for DMA-FQ, when drivers
> > are converted to use it they automatically get support.
> > 
> > Detect iommpt directly instead of using IOMMU_CAP_DEFERRED_FLUSH and
> > remove IOMMU_CAP_DEFERRED_FLUSH from converted drivers.
> > 
> > This will also enable DMA-FQ on RISC-V.
> 
> I'd much prefer to just add the cap to the RISC-V driver so it's obvious,
> rather than deliberately introduce a fiddly inconsistency. Besides, having
> iommu-dma poke directly at driver-specific internal implementation details
> seems exactly the kind of layering violation you're normally the first to
> object to.

I don't view it as a "driver-specific internal" - generic pt is part
of the core API surface. It is fine to have it and the core code be
coupled together. So I don't like bouncing through the driver to get
information the core already has direct access to...

Like the map/unmap flow run differently now for generic pt and I think
we will keep building things in. My intention is that generic pt will
be mandatory to access certain new features and functions.

But I don't care so much, we can't eliminate IOMMU_CAP_DEFERRED_FLUSH
entirely, this would have just contained it to the para-virt drivers
that can never use generic pt.

> Note that IOMMU_CAP_CACHE_COHERENCY is also arguably a property of
> generic_pt, in as much as all its users are default-coherent with
> IOMMU_CACHE implied, but again RISC_V doesn't report that where AMD and
> Intel do.

Hmm.. Currently generic_pt doesn't have any idea if IOMMU_CACHE is
supported and working in HW. All the implemented formats ignore
IOMMU_CACHE entirely, they use IOMMU_MMIO to build any any non-caching
PTE.

SMMUv3 will be unlike the other three and needs
IOMMU_CAP_CACHE_COHERENCY.  IDK if ARM should be writing non-caching
PTEs for non-coherent DMA, it doesn't now..

RISCV does seem to have some gap here.

Jason