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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?roAxOOlzbGjIgG+FrkaK3mo7Kd+hbrNEtCG9ZbXbW94ITFt3AsryC8macd/C?= =?us-ascii?Q?relqauVRAlTechJVuRksOZY+TjCsWtROis63/27fxGwVSm1n7AA39j8foVod?= =?us-ascii?Q?K12zfTnE1nzwbooxRMToptw/+h2bsOjZDvJ5KOnTNdcQR4rnmE6kD1sToOcz?= =?us-ascii?Q?iGnrxVHgwTacgQZTJYkJzWYMAqxCePfH7m+HjuSBKkwygmEeYpEwS7eMYz60?= =?us-ascii?Q?9EuLKGXEaAgCwW5OfTICiAublYY9+eFjhudc7i4oQfqKeH1mpuTQiQGxWfj8?= =?us-ascii?Q?z7x/xn52SyrzoL0uuY+fi7J+g2bdvizw8cvb9AoKCWdX/9KL9O4jVw1Jk3Wr?= =?us-ascii?Q?GRpeqy4/gWrhjypOZbMQroxfbN/hE9eyziFd8lOy2+ZpcDkUEptUlwHu19EM?= =?us-ascii?Q?NMND8lNYf9Yv99D0/vB0O7nOvBgkTnxY8CMtINVZ4gqjYvSPqmQAsFuoXuQ7?= =?us-ascii?Q?OWFvNvJICK0NUi3TFtJ37r5g8tEPCf5l1zUNi8v4UdZlDQCJBiAPEphebtjg?= =?us-ascii?Q?VXIWKKCJXF/RBd60LoJ3pXtEWpe0pI6JR+mvO+a02Wd4mwejc2PWqCbblv0T?= =?us-ascii?Q?MnPnGShPWAijvSqMuLI8nh2ZWMLcV31tm0vedx0W/I+neGvmDOhsu+Iw28ZN?= =?us-ascii?Q?X4TLtBDTbZJIE+4O5C6rXC3wuaJZKxNt5GPc5EBDT31dNz6lsNQjBZ28ApFE?= =?us-ascii?Q?wQg1TYP1BtxeqKvN3XdDVbtLahflPrWjXj6aJ0tEuprovLvuU9u4wtTfd5wu?= =?us-ascii?Q?9ubJVscVYYn0aG6ChUZRR7pF/Q8JBkig40qiht90IyyRBtGD43Nus1kMP2+d?= =?us-ascii?Q?CPbRVlmHdIlJ2NXZxguusEWvLPo1m29Szl8tYHOcDgGQ9X2b6UxW11TbU3DQ?= =?us-ascii?Q?8G84L92Q/oA3ZVQlLCA+ZIKlRx35trG8tiwvgyEcqP4x4cj8ENMouAxc1N51?= =?us-ascii?Q?XGcHO7Et+DbaSYgOQAk0VpT4dwtH4cLieYGCSJuX7vW7kPMVC5PlPTd4HQ7D?= =?us-ascii?Q?aPyHnnvvkAbVjFD5PLw7dzuDfrDC5DirqJQ8SH0+VVWTAsUSAxRGvc6Jq/jw?= =?us-ascii?Q?14BE3HiQGNgXj1vwXzmHhOfhyIU4BJBI40ab+sQ64tPpMZeWc0K2uHVuaVbW?= =?us-ascii?Q?IAbKrZL7eW1HG7hB2rAtVUX1JLHES2NUISRs3FzpOATUSR2boYyUDAle8LRH?= =?us-ascii?Q?zTwmw6po1vTSYWk46y3tPhcxwoHeyGDlOjki7bLOuRhd34BpjSR/l/Xh52DF?= =?us-ascii?Q?uhd2Na1eQ5DRs1ca92YDFPNYJ5ROtTmc3WnXPltlWCPOEGaqE4Hhn0/94D6C?= =?us-ascii?Q?AcDn0wihHaTC8De49gUGPSergpIhGQAvMhKWpmG3Ud3NWMRymJ0vdEB6Kp9y?= =?us-ascii?Q?ojcZSQEKQfIWrBNLliqb95bRE5wWaw5EhhNZS+qJO3aPFmyhENvMo+Q4Krxu?= =?us-ascii?Q?oB7/nR6GZc7upCvthtxBPmXPtUVi3eCjh+kGVJysu/LerzLkE4wzKPFplMbU?= =?us-ascii?Q?sRcugMrZCyouBPAgos96QzJLkmazLwxZLxWvfn/Ay2IbI+nrIuzYyH49zTYv?= =?us-ascii?Q?ebcNogjhEPYd4vU8tVsXsw8DMuYnPFNAOLWptsVY1EVzsJmw0FXdv5ltjvff?= =?us-ascii?Q?MqkXINHehpyYBVNltZfB0O45aY8QhP60rKXGdx9z1kmU/h/KanBQHfJGrBeE?= =?us-ascii?Q?FrYaWOdIMyeceRhCB7uqeso8CknAyU7E2UVDumumFeIgD5FK?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d33afc36-2a78-4109-4f7d-08de8ff0843f X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2026 13:13:50.8245 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WnpbBpfE7JKW+a3XralJg6hYcY7lFg+0+2ang+GQfyRnQW2Gj15cSFNOde25eXwx X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8242 On Wed, Apr 01, 2026 at 01:53:05PM +0100, Robin Murphy wrote: > On 2026-03-26 7:30 pm, Jason Gunthorpe wrote: > > iommupt always supports the semantics required for DMA-FQ, when drivers > > are converted to use it they automatically get support. > > > > Detect iommpt directly instead of using IOMMU_CAP_DEFERRED_FLUSH and > > remove IOMMU_CAP_DEFERRED_FLUSH from converted drivers. > > > > This will also enable DMA-FQ on RISC-V. > > I'd much prefer to just add the cap to the RISC-V driver so it's obvious, > rather than deliberately introduce a fiddly inconsistency. Besides, having > iommu-dma poke directly at driver-specific internal implementation details > seems exactly the kind of layering violation you're normally the first to > object to. I don't view it as a "driver-specific internal" - generic pt is part of the core API surface. It is fine to have it and the core code be coupled together. So I don't like bouncing through the driver to get information the core already has direct access to... Like the map/unmap flow run differently now for generic pt and I think we will keep building things in. My intention is that generic pt will be mandatory to access certain new features and functions. But I don't care so much, we can't eliminate IOMMU_CAP_DEFERRED_FLUSH entirely, this would have just contained it to the para-virt drivers that can never use generic pt. > Note that IOMMU_CAP_CACHE_COHERENCY is also arguably a property of > generic_pt, in as much as all its users are default-coherent with > IOMMU_CACHE implied, but again RISC_V doesn't report that where AMD and > Intel do. Hmm.. Currently generic_pt doesn't have any idea if IOMMU_CACHE is supported and working in HW. All the implemented formats ignore IOMMU_CACHE entirely, they use IOMMU_MMIO to build any any non-caching PTE. SMMUv3 will be unlike the other three and needs IOMMU_CAP_CACHE_COHERENCY. IDK if ARM should be writing non-caching PTEs for non-coherent DMA, it doesn't now.. RISCV does seem to have some gap here. Jason