Re: [PATCH 6.12 230/242] drm/amd/display: Reject modes with too high pixel clock on DCE6-10

Harshit Mogalapalli
2026-04-10T19:08:51Z

Hi,

On 08/04/26 23:34, Greg Kroah-Hartman wrote:
> #include "resource.h"
> +#include "clk_mgr.h"
> #include "include/irq_service_interface.h"
> #include "virtual/virtual_stream_encoder.h"
> #include "dce110/dce110_resource.h"
> @@ -843,10 +844,17 @@ static bool dce100_validate_bandwidth(
> {
> int i;
> bool at_least_one_pipe = false;
> + struct dc_stream_state *stream = NULL;
> + const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
>
> for (i = 0; i < dc->res_pool->pipe_count; i++) {
> - if (context->res_ctx.pipe_ctx[i].stream)
> + stream = context->res_ctx.pipe_ctx[i].stream;
> + if (stream) {
> at_least_one_pipe = true;
> +
> + if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
> + return DC_FAIL_BANDWIDTH_VALIDATE;
> + }
> }

This is a backport of commit: 118800b0797a ("drm/amd/display: Reject
modes with too high pixel clock on DCE6-10").

The backport adds return DC_FAIL_BANDWIDTH_VALIDATE, in
validate_bandwidth functions that return bool;

drivers/gpu/drm/amd/display/dc/inc/core_status.h:
DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */

In this branch DC_FAIL_BANDWIDTH_VALIDATE is integer 13, which converts
to true, so the reject path is inverted into success.

So I think we need to fix this. Thoughts ?

Maybe we need to revert this or backport commit: 4465dd0e41e8
("drm/amd/display: Refactor SubVP cursor limiting logic") to stable branch.

Thanks,
Harshit

>
> if (at_least_one_pipe) {
> --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
> @@ -32,6 +32,7 @@
> #include "stream_encoder.h"
>
> #include "resource.h"
> +#include "clk_mgr.h"
> #include "include/irq_service_interface.h"
> #include "irq/dce80/irq_service_dce80.h"
> #include "dce110/dce110_timing_generator.h"
> @@ -876,10 +877,17 @@ static bool dce80_validate_bandwidth(
> {
> int i;
> bool at_least_one_pipe = false;
> + struct dc_stream_state *stream = NULL;
> + const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
>
> for (i = 0; i < dc->res_pool->pipe_count; i++) {
> - if (context->res_ctx.pipe_ctx[i].stream)
> + stream = context->res_ctx.pipe_ctx[i].stream;
> + if (stream) {
> at_least_one_pipe = true;
> +
> + if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
> + return DC_FAIL_BANDWIDTH_VALIDATE;
> + }
> }
>
> if (at_least_one_pipe) {