From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEBBD3D669D; Tue, 16 Jun 2026 18:40:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781635215; cv=none; b=VcHYxeF8ItTKxmLkevuPqXYjC0jWgPwddCxc3/L0UjGwpZOqUv/QoGxvdOF4F6ZXheyLkbetmaW1tkMHy3sbtFa14IvErJD5BXK9OPY18cqKWQSetUub6MAaAm/8LRxVIPLQmnSM6oUPGmMroaMCQVr8fPhdyMSlFxa0FVyAowQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781635215; c=relaxed/simple; bh=TOTyKVEsMaQ8KF8AYxcDvrQ6U3nEJuZ6oItZ4YehWYE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X4c6kL6ch1ykA3ZsM6ODQAXgGnODYaraLzQziA3TAPSKE9YphaqIMc+AemJmcHIRADYVksUuGYVZ9O/Q11OEl5NrjteruZvihY5pylj7uz/0LhMWKCGOPZD/oyD8AzRbOQh7n3fB94VEjDIYPQtqx6JxurrZy4HxbdQcejAHxDg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=OA0lvGX2; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="OA0lvGX2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DFFDE1F000E9; Tue, 16 Jun 2026 18:40:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1781635214; bh=SaAq0ByqDeG39gI7XuPgtEhIWwz6N+g6RkKLxqgopYs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=OA0lvGX24s2zuXEMiuonwnheta3wSTIVZnqKfALrEB0JVjFCgF4SV4XqZqO02xYWz yvMGtEBpMp9YmselC/+H0cHutfLLaShMqYi1j/p9Y80RrfJcgyGRT1LT9JLA28BHIX rrwdp4bny2sndmcoD698oBjsQbKCjPkShHBt/zw0= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Shanker Donthineni , Will Deacon , Mark Rutland Subject: [PATCH 5.15 402/411] arm64: cputype: Add NVIDIA Olympus definitions Date: Tue, 16 Jun 2026 20:30:40 +0530 Message-ID: <20260616145122.541481793@linuxfoundation.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260616145100.376842714@linuxfoundation.org> References: <20260616145100.376842714@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Shanker Donthineni commit e185c8a0d84236d14af61faff8147c953a878a77 upstream. Add cpu part and model macro definitions for NVIDIA Olympus core. Signed-off-by: Shanker Donthineni Signed-off-by: Will Deacon [Mark: backport to v5.15.y] Signed-off-by: Mark Rutland Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -121,6 +121,7 @@ #define NVIDIA_CPU_PART_DENVER 0x003 #define NVIDIA_CPU_PART_CARMEL 0x004 +#define NVIDIA_CPU_PART_OLYMPUS 0x010 #define FUJITSU_CPU_PART_A64FX 0x001 @@ -183,6 +184,7 @@ #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) +#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)