From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F23D33FFFAF; Tue, 21 Jul 2026 17:45:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784655907; cv=none; b=V9Zw4OA4B1QABELcA0440zq9P3yAWQDmKhUWj0orClHRjIdpKfdioDqD1uoJCmeuoCrnwLDGVbv5LcTVM/QQLBWe5YLiMOHtxUZn74WyaXg8PbDNFooI2Z4Hng7/r7PRfa759IHYd2GNgeSxYS6ZM+lLOs3xcxzQHUrAhGIwqMo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784655907; c=relaxed/simple; bh=jUIhWW99I0F7lfZ8P9LUHzLzzKhWYh3FE0SQgV1sfFo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XiPWENuQWlRWE7qBGOfePqwrFc41l3eaj9Vwax7J9s5cVml7uiSUzzkUrJ1T42/kDtOQZpMmmb8eK4IjHo+yLHF+UFFN/LtDweq0N4hTOtFwqmEvgF/MzpdbQ118ldSs5Yn432hFvlkOTOtj7su1d/Rndfp5QzVacvR+cAcPzwE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=WEcBHLni; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="WEcBHLni" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 641161F000E9; Tue, 21 Jul 2026 17:45:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784655905; bh=A06JmlKAkr0WVxxSAnMTldbOVE1q4cULPlWIROXgkUU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WEcBHLniYKB68/grpSTwtrfKHj+hwj9XgZkQGX3/UmFuyOmnMeiBNgS1qhY330xp3 ALoeM19zzljb5HpgPjmnP1PB0HHSBsV+qZqH1mTaSgT75IHQJ4QpQmnUeiMv7ttv+7 +59thQyNZ2OrVz1bLV+mqugPJUOHtAPNkhum/b+4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Kuldeep Singh , Harshal Dev , Bjorn Andersson , Sasha Levin Subject: [PATCH 6.18 0184/1611] arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node Date: Tue, 21 Jul 2026 17:05:00 +0200 Message-ID: <20260721152519.065427584@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260721152514.750365251@linuxfoundation.org> References: <20260721152514.750365251@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Harshal Dev [ Upstream commit 68d5d9701a7ab1b1f9c76feaa3a24ca716f03f0b ] Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for monaco. Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-5-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 8580884a16e98b..501814babed15e 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2351,7 +2351,11 @@ ice: crypto@1d88000 { compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { -- 2.53.0