From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 053CF405845; Tue, 21 Jul 2026 17:45:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784655915; cv=none; b=Kk7pFE34QEWjwEQh9+gLxqj2N1KV7RqscTDqQzs9kaGV8P1FmjaIr72DLQdC20DBX4kUPisBtINJL/kKIuPpOKso81CVcqxJG4OxwqugsEnNnQsRGnVAmA+4GmJ1nKVeYL2dT9SAw3nc1Q9zdyrvjCi6hvF4S3mLkmLsWhJ0Ei8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784655915; c=relaxed/simple; bh=kX+0h6O+K5t3+rpGJtBlvWMWN2u4Drw+3O3TJ7kbAFc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mefDUSPnibiiXPHePLj3TiDZtZL8DKOCNWQsJKfvLjMIJ/kZ8wqHEXiUNV8Mzi1zCSEfzgGkLEslzTl6Pn4xmTQdYM5FHB/ACigx+6r+3+NbAUlHZtsc0FhF5QQJy5Jyc5IQfTJHQSqmVE4Cm2oRk2Zy0ZG84sfhmn6kFHr5jy8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=eOdiZ2Yw; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="eOdiZ2Yw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B8F01F000E9; Tue, 21 Jul 2026 17:45:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784655913; bh=xnjZmqMYlux37MtOFVIm/a9C7WFs4F5Ce7utDbzS+hs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=eOdiZ2YwkaohwB5AkvpUlzFb59JLJNlN0A48WuQ1udfFdSqDe5spJQ/4uj7khxDqf PdwEEV4m9YxAfqpi3amv0SuAx6upwZoedRs1IaDbuQqD67XcTIIgpKQpmb2vz+rTU5 PlVAs/lDPd8VJPMeSescH/i454ZluPUGResh3/j8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Kuldeep Singh , Harshal Dev , Bjorn Andersson , Sasha Levin Subject: [PATCH 6.18 0187/1611] arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Date: Tue, 21 Jul 2026 17:05:03 +0200 Message-ID: <20260721152519.144108013@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260721152514.750365251@linuxfoundation.org> References: <20260721152514.750365251@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Harshal Dev [ Upstream commit 3a5cb1ccbfb3141862b28f24cd5050083233aae7 ] Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-8-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 3a352e5f3f191b..2d49df7b69e4b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5349,7 +5349,11 @@ ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { -- 2.53.0