From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0AD946D57E; Tue, 21 Jul 2026 15:44:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784648641; cv=none; b=Z3wtgp65RhObU/5DaRAfKlBmgnOXy4jHkGdyvq8osz6zo0eh9xYqaRocitnbXH22swCRW+1GuWXSAAhr03B2MFK/zEdfes6KbB0/jjYYYgFd8khEBvTf5pQLrdfmlh4rOLl7d0DqPkwtQdgi/FDbaaO7m5MhFv+Dw1p+qEONnLE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784648641; c=relaxed/simple; bh=Rv7C1sXhvURcjD4c6FoTZvf4q1Lmd2mWyof7+je7FA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CDCrVAyRikxW1+kU5qUQQLKLOrX9NkQ9jfJ0qwobFzRo10P9z/wF0+d2dRJInipyPm3vcS/1eWmGF5WH2pu7xES0l3eDfFz64qVlVOW13GwlLM1oUMi+D3viYkM+vaqUXXYl1xwqKgiqDqpuLo+qelYHoBgt4r6RdQ/kj/N8lBQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=hgQ9mhnh; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="hgQ9mhnh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D82BE1F00A3A; Tue, 21 Jul 2026 15:43:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784648640; bh=cuTGakr+E43JGf0ztkKfptApr8SDBzDAnRBEpC+a3wE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hgQ9mhnhDN9sokAWThMYk9ndMm4x3Vcact5j1RY/ReM+hVICg0DxB0teq2bLTIRU2 HnRqq1ueTT6S4VDppbg+gk/Epd/LUxW56f7M3sqHh9t0UMkf5m2/DVh2TVVnPdMamR 6jvcK9STozw1UcE6DJqy2aG7DgmBKf7EqwOZMYAs= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Kuldeep Singh , Harshal Dev , Bjorn Andersson , Sasha Levin Subject: [PATCH 7.1 0269/2077] arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Date: Tue, 21 Jul 2026 16:59:02 +0200 Message-ID: <20260721152559.020409307@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260721152552.646164743@linuxfoundation.org> References: <20260721152552.646164743@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Harshal Dev [ Upstream commit 3a5cb1ccbfb3141862b28f24cd5050083233aae7 ] Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-8-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e0c37ce3042a22..47b028259d9101 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5374,7 +5374,11 @@ ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { -- 2.53.0