From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E91446D560; Tue, 21 Jul 2026 15:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784648670; cv=none; b=RRzEuAVp+6ZnsGHWpb+XA18WPdXBfgmsfQkoCdC7xYg3+Km7NHIPztwCEO8ZpBORbDuCpT7JR+fjuFIfnQq87IlezE58sdREhkDaO7dyVoXPhnG92Lpe3T6EMb6qTdFDxak3ujs39gvycsrpddL9yG6SuivNUnA7G/eMT1MoR20= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784648670; c=relaxed/simple; bh=zSmTTVR0LjNfZHN92pqBHh5EnGFXpoC7Amb/xyxq5NQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qrVLADR0FfDQxkXBPvzwz32q14DxFfLINOp43bWqRnAlFpFIlwWeaqrCJd+YWJaIY4ceHAfgV90rGE2N+SYCwnMGyzuBVaugc2g0CpiCucQe2DbBiM0hW7acMVH+y5cq1/qm0VhtAifgMq6QPjgpKV447eDEvgxuIhZTBimMS+8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=VF+qFftG; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="VF+qFftG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F3011F000E9; Tue, 21 Jul 2026 15:44:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784648669; bh=cbGIOFrB6hPIJgXvgpXmMxJ79XIrXmOG5y+KlM5icKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VF+qFftGkVO+HlQskJsxvD2aJRwMEVFLJdH6CFIWOox77t9gD3h8cTtoVPVD/369w BOUE0Lh6lTPzb/TlDeDDfsLIn86BKvvs6UMMGx0gj21iY/OgWen+FruCGVH/NjhCL6 PmFS0ZBWMjQ08O3e5EkFXr91CBB7y651mLvfrIjY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Kuldeep Singh , Harshal Dev , Bjorn Andersson , Sasha Levin Subject: [PATCH 7.1 0270/2077] arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node Date: Tue, 21 Jul 2026 16:59:03 +0200 Message-ID: <20260721152559.045289968@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260721152552.646164743@linuxfoundation.org> References: <20260721152552.646164743@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Harshal Dev [ Upstream commit 52696dbbe7bbe0c8fc8c17133ffb5133b8cf37a6 ] Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550. Fixes: b8630c48b43fc ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-9-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 912525e9bca6f5..fe46a5d41fe072 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2465,7 +2465,11 @@ ice: crypto@1d88000 { "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { -- 2.53.0