From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D979C43C04B; Thu, 30 Jul 2026 16:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785427305; cv=none; b=sNBFjiibZNOxXiDDXcdH6jZcUgMdLD2EkUsOFqzYV0GaJ3lPfvtsnJi/W5fo3+llxLZ6Lfld18dbnB96D/5Sm36hwlOiQq2DDIn5UrCh4ttxefu7zrOrgycOcwdZzHbvWeGCpI31jECke0H/VVV0NYS7OvKS4OU8DodBhsmV4Pk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785427305; c=relaxed/simple; bh=11KK96qVy4478ULemsH5C0xtCRtQWLjQ7RlXU8im8iw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MTXsQJFkr8xI6A1V1PWM+OpsSjEus47XtqaN0uTfSpE4lNQPjf8v/sQgLod1M0xyMaH5ty5tVDLxKReHaRAlLM7uu0prCdETpoak0is1zRg8UqULZNqwjYI2TZxL8PfOsWIa9PAgUR6eEN3a0U4bGtbaNfXGM9zt8FM2ZspysVg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=DYDPnePQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="DYDPnePQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F39E01F00A3A; Thu, 30 Jul 2026 16:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1785427303; bh=EDwiXYKkGK738XskToK/cTnRZQvEV2njd5hAoKABr9U=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=DYDPnePQCuThRZz+YTA9DccguXJTnEuqU26G99fjHIGsOPS7nCJPmmUAOdu0hpJpM lWA8yTwNwSXSiDou2dq+vc1szisrm5SUvZ805sLhdmhSV01VtSAISO4Clnl3Yf34Gf 9F4hDltIxlcPrtxpUJ/6VKYhxTTkI6gWleRfWtA8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Alex Williamson , Manivannan Sadhasivam , Baochen Qiang , Raj Kumar Bhagat , Jeff Johnson , Sasha Levin Subject: [PATCH 6.6 122/484] wifi: ath11k: Flush the posted write after writing to PCIE_SOC_GLOBAL_RESET Date: Thu, 30 Jul 2026 16:10:19 +0200 Message-ID: <20260730141426.110296026@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260730141423.392222816@linuxfoundation.org> References: <20260730141423.392222816@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Manivannan Sadhasivam [ Upstream commit 0fe8010fc5b147607fc19ba010ba469afc95f35f ] ath11k_pci_soc_global_reset() tries to reset the device by writing to the PCIE_SOC_GLOBAL_RESET register. But it doesn't do a read-back to ensure that the write gets flushed to the device before the delay. This may lead to the delay on the host to be insufficient, if the posted write doesn't reach the device before the delay. So add a read-back after writing to the PCIE_SOC_GLOBAL_RESET register and before the delay. Compile tested only. Fixes: f3c603d412b3 ("ath11k: reset MHI during power down and power up") Reported-by: Alex Williamson Closes: https://lore.kernel.org/linux-pci/20260622160822.09350246@shazbot.org Signed-off-by: Manivannan Sadhasivam Reviewed-by: Baochen Qiang Reviewed-by: Raj Kumar Bhagat Link: https://patch.msgid.link/20260623141649.41087-1-manivannan.sadhasivam@oss.qualcomm.com Signed-off-by: Jeff Johnson Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath11k/pci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c index 09e65c5e55c4a9..966ba712ff9094 100644 --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c @@ -181,6 +181,8 @@ static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) val |= PCIE_SOC_GLOBAL_RESET_V; ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); + /* Flush the posted write to the device */ + ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); /* TODO: exact time to sleep is uncertain */ delay = 10; @@ -190,6 +192,8 @@ static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) val &= ~PCIE_SOC_GLOBAL_RESET_V; ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); + /* Flush the posted write to the device */ + ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); mdelay(delay); -- 2.53.0