From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFF18364028; Fri, 7 Aug 2026 15:45:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786117527; cv=none; b=HaovNIWwVi6Pl6J+ljqlt12KjqNRCNj6Oe7/OpioyKSM1fUAPEB2qvyS71Tk6m9/eHFeB56gfpATLthvDdwyUzRDuc8QCLXAGwOW2duCKGw7EMwfHekZdi+CyT34li1YaruTYZm7v7sR6ucbZpZbTxMyr6VLA00Iye8OPSyCebs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786117527; c=relaxed/simple; bh=GO73DdRC0qxwdlYApACjRdqZFStdptzexMsAUSfSaNU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CcNgDV8zprcR/nFGFCODMLumunqZ3QUydD3odMqEe0vyZOKZUSO8qI16Z3g6VACHkwOI7gmnjncYFFk08XCgTG1fMlrE3wLBDzxRuXs/lIKZ5veNAVJT1DaBToCJIs8UvMeENacsZKHWJNNNWAak08jTHhNzFyDeNWtN3iMEcnY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=w1WB0njm; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="w1WB0njm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F0FB1F000E9; Fri, 7 Aug 2026 15:45:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1786117526; bh=Rc3R67SSZvBxsSCy2cnlImZPYCAz5xmEKCveS+tZMeQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=w1WB0njmkpoY7Myws9K2QciaYSkoCAch7OF/Io+3+CIxaaj54vrsRMTvT9ycfQTA+ 8t4VCcHHiFDNyvUiFmEB5ASqlu3KJMwCLxZAznC2Df4DNoXdJAbYze+1vR5mvYGvky CNoDDaUNg+7KPrEXnntTZFVfARlVuwWLgTMRpw8w= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Nava kishore Manne , Radhey Shyam Pandey , Michal Simek , Vinod Koul Subject: [PATCH 7.1 348/438] phy: zynqmp: use read-modify-write for SERDES scrambler bypass Date: Fri, 7 Aug 2026 16:39:04 +0200 Message-ID: <20260807143435.392054666@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260807143428.008222056@linuxfoundation.org> References: <20260807143428.008222056@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Nava kishore Manne commit 21e0749f931702765b9d52d05740092bc87fcd8d upstream. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which performs a full register write, silently clearing any bits beyond the intended bypass control fields. Switch to xpsgtr_clr_set_phy() with clr=mask, set=mask to set only the bypass bits while preserving the remaining bits in each register. Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver") Cc: stable@vger.kernel.org Signed-off-by: Nava kishore Manne Signed-off-by: Radhey Shyam Pandey Acked-by: Michal Simek Link: https://patch.msgid.link/20260627155229.2791113-3-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/phy/xilinx/phy-zynqmp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -505,8 +505,12 @@ static void xpsgtr_lane_set_protocol(str /* Bypass (de)scrambler and 8b/10b decoder and encoder. */ static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy) { - xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER); - xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER); + xpsgtr_clr_set_phy(gtr_phy, L0_TM_DIG_6, + L0_TM_DIS_DESCRAMBLE_DECODER, + L0_TM_DIS_DESCRAMBLE_DECODER); + xpsgtr_clr_set_phy(gtr_phy, L0_TX_DIG_61, + L0_TM_DISABLE_SCRAMBLE_ENCODER, + L0_TM_DISABLE_SCRAMBLE_ENCODER); } /* DP-specific initialization. */