From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C98C34749F6; Fri, 7 Aug 2026 15:49:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786117773; cv=none; b=rhiakS2MSISl7ocv78jzWeaj4L1xmK1gONkB4jKB7tO0Eg9G97Lp6Xeq/y6NCSUANZT/DiEw1tfyZZb8Dkamkr9c5e0smMc0DGnxtfEQHvA8cvGERfQGdCnBMZ4SHhlDhiJ6k0KXc/866QeS65faBMVuReSvkwvUNS8IvVZzDwg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786117773; c=relaxed/simple; bh=4M5sponoq4LTB5bbt82gtTckqjYLPP6W7X4B97yzlHE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G8uHaD/YgBX6aNbYF8sOCy5U8w0DJT1Lyw4PWYfkxGpc3ukrNlkleSz/EjGR9SaU9TfwoQpYPQqMxR5qOq90VOg55DZGdH8JNvkvAF64cLtm+JV/TTST7X7/WkIkeeTZz/5OsLlJmATtvAnogack2QNMJEUqSVnZ69s7ajCZ3a8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=B3Su1np/; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="B3Su1np/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 36C071F000E9; Fri, 7 Aug 2026 15:49:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1786117771; bh=WdvHGdDEgnbIhRFJ4/oWFkeeFYhFsG9354KtlIPY4Mo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=B3Su1np/s8VLIiH4jqy2ae3lf1Ux1Gg0hLJSr9+6ZztXq4cW5c5RhCU+Rpo0zwgPl hJtK7Reb2OZqsT1lyhzetCV6DQGq61M29P+l85Ai+rGvg34IUXyv7MlYQMbWeeuRhL OEtUMTOYG1+ZTAeMmV3GeNv73m3fhPrU3xEQ/17Y= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jackson Lee , Nas Chung , Brandon Brnich , Nicolas Dufresne , Hans Verkuil , Sasha Levin Subject: [PATCH 7.1 435/438] media: chips-media: wave5: Support CBP profile Date: Fri, 7 Aug 2026 16:40:31 +0200 Message-ID: <20260807143437.245164353@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260807143428.008222056@linuxfoundation.org> References: <20260807143428.008222056@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jackson Lee [ Upstream commit f8505f9d6b223a26854003bfdba1a0772457886d ] Constrained Baseline Profile (CBP) and Baseline Profile (BP) have been treated as the same. Introduce the ability to differentiate between the two. Fixes: 9707a6254a8a ("media: chips-media: wave5: Add the v4l2 layer") Cc: stable@vger.kernel.org Signed-off-by: Jackson Lee Signed-off-by: Nas Chung Tested-by: Brandon Brnich Reviewed-by: Nicolas Dufresne Signed-off-by: Nicolas Dufresne Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/media/platform/chips-media/wave5/wave5-hw.c | 3 +++ drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 5 ++++- drivers/media/platform/chips-media/wave5/wave5-vpuapi.h | 1 + 3 files changed, 8 insertions(+), 1 deletion(-) --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -1762,6 +1762,9 @@ int wave5_vpu_enc_init_seq(struct vpu_in (p_param->skip_intra_trans << 25) | (p_param->strong_intra_smooth_enable << 27) | (p_param->en_still_picture << 30); + else if (inst->std == W_AVC_ENC) + reg_val |= (p_param->constraint_set1_flag << 29); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val); reg_val = (p_param->lossless_enable) | --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -915,6 +915,8 @@ static int wave5_vpu_enc_s_ctrl(struct v case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: inst->enc_param.profile = H264_PROFILE_BP; inst->bit_depth = 8; + if (ctrl->val == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) + inst->enc_param.constraint_set1_flag = 1; break; case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: inst->enc_param.profile = H264_PROFILE_MP; @@ -1190,6 +1192,7 @@ static int wave5_set_enc_openparam(struc open_param->wave_param.intra_period = input.avc_idr_period; } } else { + open_param->wave_param.constraint_set1_flag = input.constraint_set1_flag; open_param->wave_param.avc_idr_period = input.avc_idr_period; } open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode; @@ -1662,7 +1665,7 @@ static int wave5_vpu_open_enc(struct fil -6, 6, 1, 0); v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, - 0, 1, 1, 1); + 0, 1, 1, 0); v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION, 0, 1, 1, 0); --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -570,6 +570,7 @@ struct enc_wave_param { u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */ u32 mb_level_rc_enable: 1; /* enable MB-level rate control */ u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */ + u32 constraint_set1_flag: 1; /* enable CBP */ }; struct enc_open_param {