From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: stable@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
patches@lists.linux.dev, Dillon Varone <dillon.varone@amd.com>,
Gaghik Khachatrian <gaghik.khachatrian@amd.com>,
James Lin <pinglei.lin@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Sasha Levin <sashal@kernel.org>
Subject: [PATCH 7.1 151/228] drm/amd/display: Fix type mismatches in DML and normalize loop bounds
Date: Thu, 20 Aug 2026 16:54:53 +0200 [thread overview]
Message-ID: <20260820145249.225110052@linuxfoundation.org> (raw)
In-Reply-To: <20260820145244.450574346@linuxfoundation.org>
7.1-stable review patch. If anyone has any objections, please let me know.
------------------
From: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
[ Upstream commit faaeeecef94ad312b051dbe628d6e3f016ba5263 ]
[Why]
Address signed/unsigned comparison warnings across DML paths
to keep builds warning-clean and improve type safety at comparison
boundaries. Most warnings came from signed loop/index temporaries compared
against unsigned counters (for example pipe_count, num_states, and
candidate/state counts), plus a small number of mixed signed/unsigned
clock and geometry checks.
[How]
Aligned iterator and temporary variable types with the semantic type
of the compared bounds. Used unsigned indices for loops bounded by unsigned
counters, and retained signed types where values are semantically signed
(for example plane_count math, timing/micro-schedule arithmetic, and
reverse/sentinel-style iteration). Where mixed signed/unsigned comparisons
are intentional, applied explicit boundary casts instead of broad type
changes (for example dispclk minimum clamp and selected timing/height
comparisons).
As a side effect of converting count parameters such as
NumberOfActivePlanes to unsigned, normalized equivalent loop forms from:
for (i = 0; i <= NumberOfActivePlanes - 1; i++)
into the normalized form:
for (i = 0; i < NumberOfActivePlanes; i++)
to keep bound style coherent and avoid avoidable mismatch patterns.
No functional behavior changes are intended; this is a warning-resolution
and type-alignment cleanup.
Assisted-by: Copilot
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: 93c8fe6d5603 ("drm/amd/display: guard against overflow in HDCP message dump")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 9
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 34 +-
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 36 +-
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 36 +-
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 36 +-
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 14 -
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 83 +++---
drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 5
drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c | 2
drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c | 2
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 15 -
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 121 +++++----
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 5
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 129 +++++-----
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 75 +++--
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 21 -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 46 +--
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 5
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 5
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4
21 files changed, 366 insertions(+), 319 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -759,7 +759,8 @@ bool dcn_validate_bandwidth(
const struct resource_pool *pool = dc->res_pool;
struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
- int i, input_idx, k;
+ unsigned int i;
+ int input_idx, k;
int vesa_sync_start, asic_blank_end, asic_blank_start;
bool bw_limit_pass;
float bw_limit;
@@ -1168,9 +1169,9 @@ bool dcn_validate_bandwidth(
context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
- dc->debug.min_disp_clk_khz) {
+ (int)dc->debug.min_disp_clk_khz) {
context->bw_ctx.bw.dcn.clk.dispclk_khz =
- dc->debug.min_disp_clk_khz;
+ (int)dc->debug.min_disp_clk_khz;
}
context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
@@ -1307,7 +1308,7 @@ bool dcn_validate_bandwidth(
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
- if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))
+ if (bw_limit_pass && v->voltage_level <= (int)get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))
return true;
else
return false;
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -990,7 +990,8 @@ void dcn20_populate_dml_writeback_from_c
struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes)
{
- int pipe_cnt, i;
+ unsigned int i;
+ int pipe_cnt;
dc_assert_fp_enabled();
@@ -1044,7 +1045,7 @@ void dcn20_fpu_set_wb_arb_params(struct
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
@@ -1134,7 +1135,7 @@ static void dcn20_adjust_freesync_v_star
/* The newVStartUp is 1 line before vsync point */
newVstartup = asic_blank_end + 1;
- *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
+ *vstartup_start = (((int)newVstartup > *vstartup_start) ? (int)newVstartup : *vstartup_start);
}
void dcn20_calculate_dlg_params(struct dc *dc,
@@ -1143,7 +1144,8 @@ void dcn20_calculate_dlg_params(struct d
int pipe_cnt,
int vlevel)
{
- int i, pipe_idx, active_hubp_count = 0;
+ int pipe_idx, active_hubp_count = 0;
+ unsigned int i;
dc_assert_fp_enabled();
@@ -1155,7 +1157,7 @@ void dcn20_calculate_dlg_params(struct d
context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
- if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
+ if ((int)dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
@@ -1173,8 +1175,8 @@ void dcn20_calculate_dlg_params(struct d
context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
- if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
- context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
+ if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
+ context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz;
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
@@ -1317,7 +1319,8 @@ int dcn20_populate_dml_pipes_from_contex
enum dc_validate_mode validate_mode)
{
(void)validate_mode;
- int pipe_cnt, i;
+ int pipe_cnt;
+ unsigned int i;
bool synchronized_vblank = true;
struct resource_context *res_ctx = &context->res_ctx;
@@ -1735,7 +1738,8 @@ void dcn20_calculate_wm(struct dc *dc, s
int vlevel,
enum dc_validate_mode validate_mode)
{
- int pipe_cnt, i, pipe_idx;
+ int pipe_cnt, pipe_idx;
+ unsigned int i;
dc_assert_fp_enabled();
@@ -1853,7 +1857,7 @@ void dcn20_update_bounding_box(struct dc
{
int num_calculated_states = 0;
int min_dcfclk = 0;
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
@@ -1914,7 +1918,7 @@ void dcn20_update_bounding_box(struct dc
void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks)
{
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
@@ -2158,7 +2162,7 @@ int dcn21_populate_dml_pipes_from_contex
enum dc_validate_mode validate_mode)
{
uint32_t pipe_cnt;
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
@@ -2240,7 +2244,8 @@ static void dcn21_calculate_wm(struct dc
int vlevel_req,
enum dc_validate_mode validate_mode)
{
- int pipe_cnt, i, pipe_idx;
+ int pipe_cnt, pipe_idx;
+ unsigned int i;
int vlevel, vlevel_max;
struct wm_range_table_entry *table_entry;
struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
@@ -2476,7 +2481,8 @@ void dcn201_populate_dml_writeback_from_
struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes)
{
- int pipe_cnt, i, j;
+ int pipe_cnt;
+ unsigned int i, j;
double max_calc_writeback_dispclk;
double writeback_dispclk;
struct writeback_st dout_wb = {0};
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -3288,8 +3288,8 @@ void dml20_ModeSupportAndSystemConfigura
{
struct vba_vars_st *locals = &mode_lib->vba;
- int i;
- unsigned int j, k, m;
+ int idx;
+ unsigned int i, j, k, m;
/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
@@ -5018,7 +5018,7 @@ void dml20_ModeSupportAndSystemConfigura
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
+ for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
@@ -5026,21 +5026,21 @@ void dml20_ModeSupportAndSystemConfigura
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (locals->ViewportSizeSupport[i][0] != true) {
+ } else if (locals->ViewportSizeSupport[idx][0] != true) {
status = DML_FAIL_VIEWPORT_SIZE;
- } else if (locals->DIOSupport[i] != true) {
+ } else if (locals->DIOSupport[idx] != true) {
status = DML_FAIL_DIO_SUPPORT;
- } else if (locals->NotEnoughDSCUnits[i] != false) {
+ } else if (locals->NotEnoughDSCUnits[idx] != false) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
+ } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) {
status = DML_FAIL_DSC_CLK_REQUIRED;
- } else if (locals->UrgentLatencySupport[i][j] != true) {
+ } else if (locals->UrgentLatencySupport[idx][j] != true) {
status = DML_FAIL_URGENT_LATENCY;
- } else if (locals->ROBSupport[i][0] != true) {
+ } else if (locals->ROBSupport[idx][0] != true) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
+ } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (locals->TotalAvailablePipesSupport[i][j] != true) {
+ } else if (locals->TotalAvailablePipesSupport[idx][j] != true) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (mode_lib->vba.NumberOfOTGSupport != true) {
status = DML_FAIL_NUM_OTG;
@@ -5054,24 +5054,24 @@ void dml20_ModeSupportAndSystemConfigura
status = DML_FAIL_CURSOR_SUPPORT;
} else if (mode_lib->vba.PitchSupport != true) {
status = DML_FAIL_PITCH_SUPPORT;
- } else if (locals->PrefetchSupported[i][j] != true) {
+ } else if (locals->PrefetchSupported[idx][j] != true) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) {
+ } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (locals->VRatioInPrefetchSupported[i][j] != true) {
+ } else if (locals->VRatioInPrefetchSupported[idx][j] != true) {
status = DML_FAIL_V_RATIO_PREFETCH;
- } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
+ } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
status = DML_FAIL_DSC_INPUT_BPC;
}
if (status == DML_VALIDATION_OK) {
- locals->ModeSupport[i][j] = true;
+ locals->ModeSupport[idx][j] = true;
} else {
- locals->ModeSupport[i][j] = false;
+ locals->ModeSupport[idx][j] = false;
}
- locals->ValidationStatus[i] = status;
+ locals->ValidationStatus[idx] = status;
}
}
{
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -3396,8 +3396,8 @@ void dml20v2_ModeSupportAndSystemConfigu
{
struct vba_vars_st *locals = &mode_lib->vba;
- int i;
- unsigned int j, k, m;
+ int idx;
+ unsigned int i, j, k, m;
/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
@@ -5135,7 +5135,7 @@ void dml20v2_ModeSupportAndSystemConfigu
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
+ for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
@@ -5143,21 +5143,21 @@ void dml20v2_ModeSupportAndSystemConfigu
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (locals->ViewportSizeSupport[i][0] != true) {
+ } else if (locals->ViewportSizeSupport[idx][0] != true) {
status = DML_FAIL_VIEWPORT_SIZE;
- } else if (locals->DIOSupport[i] != true) {
+ } else if (locals->DIOSupport[idx] != true) {
status = DML_FAIL_DIO_SUPPORT;
- } else if (locals->NotEnoughDSCUnits[i] != false) {
+ } else if (locals->NotEnoughDSCUnits[idx] != false) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
+ } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) {
status = DML_FAIL_DSC_CLK_REQUIRED;
- } else if (locals->UrgentLatencySupport[i][j] != true) {
+ } else if (locals->UrgentLatencySupport[idx][j] != true) {
status = DML_FAIL_URGENT_LATENCY;
- } else if (locals->ROBSupport[i][0] != true) {
+ } else if (locals->ROBSupport[idx][0] != true) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
+ } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (locals->TotalAvailablePipesSupport[i][j] != true) {
+ } else if (locals->TotalAvailablePipesSupport[idx][j] != true) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (mode_lib->vba.NumberOfOTGSupport != true) {
status = DML_FAIL_NUM_OTG;
@@ -5171,24 +5171,24 @@ void dml20v2_ModeSupportAndSystemConfigu
status = DML_FAIL_CURSOR_SUPPORT;
} else if (mode_lib->vba.PitchSupport != true) {
status = DML_FAIL_PITCH_SUPPORT;
- } else if (locals->PrefetchSupported[i][j] != true) {
+ } else if (locals->PrefetchSupported[idx][j] != true) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) {
+ } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (locals->VRatioInPrefetchSupported[i][j] != true) {
+ } else if (locals->VRatioInPrefetchSupported[idx][j] != true) {
status = DML_FAIL_V_RATIO_PREFETCH;
- } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
+ } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
status = DML_FAIL_DSC_INPUT_BPC;
}
if (status == DML_VALIDATION_OK) {
- locals->ModeSupport[i][j] = true;
+ locals->ModeSupport[idx][j] = true;
} else {
- locals->ModeSupport[i][j] = false;
+ locals->ModeSupport[idx][j] = false;
}
- locals->ValidationStatus[i] = status;
+ locals->ValidationStatus[idx] = status;
}
}
{
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -3525,8 +3525,8 @@ void dml21_ModeSupportAndSystemConfigura
{
struct vba_vars_st *locals = &mode_lib->vba;
- int i;
- unsigned int j, k, m;
+ int idx;
+ unsigned int i, j, k, m;
/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
@@ -5138,7 +5138,7 @@ void dml21_ModeSupportAndSystemConfigura
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
+ for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
@@ -5146,19 +5146,19 @@ void dml21_ModeSupportAndSystemConfigura
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (!mode_lib->vba.SourceFormatPixelAndScanSupport) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (!locals->ViewportSizeSupport[i][0]) {
+ } else if (!locals->ViewportSizeSupport[idx][0]) {
status = DML_FAIL_VIEWPORT_SIZE;
- } else if (!locals->DIOSupport[i]) {
+ } else if (!locals->DIOSupport[idx]) {
status = DML_FAIL_DIO_SUPPORT;
- } else if (locals->NotEnoughDSCUnits[i]) {
+ } else if (locals->NotEnoughDSCUnits[idx]) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (locals->DSCCLKRequiredMoreThanSupported[i]) {
+ } else if (locals->DSCCLKRequiredMoreThanSupported[idx]) {
status = DML_FAIL_DSC_CLK_REQUIRED;
- } else if (!locals->ROBSupport[i][0]) {
+ } else if (!locals->ROBSupport[idx][0]) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (!locals->DISPCLK_DPPCLK_Support[i][j]) {
+ } else if (!locals->DISPCLK_DPPCLK_Support[idx][j]) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (!locals->TotalAvailablePipesSupport[i][j]) {
+ } else if (!locals->TotalAvailablePipesSupport[idx][j]) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (!mode_lib->vba.NumberOfOTGSupport) {
status = DML_FAIL_NUM_OTG;
@@ -5172,27 +5172,27 @@ void dml21_ModeSupportAndSystemConfigura
status = DML_FAIL_CURSOR_SUPPORT;
} else if (!mode_lib->vba.PitchSupport) {
status = DML_FAIL_PITCH_SUPPORT;
- } else if (!locals->TotalVerticalActiveBandwidthSupport[i][0]) {
+ } else if (!locals->TotalVerticalActiveBandwidthSupport[idx][0]) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (!locals->PTEBufferSizeNotExceeded[i][j]) {
+ } else if (!locals->PTEBufferSizeNotExceeded[idx][j]) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (mode_lib->vba.NonsupportedDSCInputBPC) {
status = DML_FAIL_DSC_INPUT_BPC;
} else if ((mode_lib->vba.HostVMEnable
- && !locals->ImmediateFlipSupportedForState[i][j])) {
+ && !locals->ImmediateFlipSupportedForState[idx][j])) {
status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
- } else if (!locals->PrefetchSupported[i][j]) {
+ } else if (!locals->PrefetchSupported[idx][j]) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (!locals->VRatioInPrefetchSupported[i][j]) {
+ } else if (!locals->VRatioInPrefetchSupported[idx][j]) {
status = DML_FAIL_V_RATIO_PREFETCH;
}
if (status == DML_VALIDATION_OK) {
- locals->ModeSupport[i][j] = true;
+ locals->ModeSupport[idx][j] = true;
} else {
- locals->ModeSupport[i][j] = false;
+ locals->ModeSupport[idx][j] = false;
}
- locals->ValidationStatus[i] = status;
+ locals->ValidationStatus[idx] = status;
}
}
{
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -181,7 +181,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3
void dcn30_fpu_populate_dml_writeback_from_context(
struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
{
- int pipe_cnt, i, j;
+ int pipe_cnt;
+ unsigned int i, j;
double max_calc_writeback_dispclk;
double writeback_dispclk;
struct writeback_st dout_wb = {0};
@@ -308,6 +309,7 @@ void dcn30_fpu_calculate_wm_and_dlg(
{
int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
int i, pipe_idx;
+ unsigned int pipe_i, state_i;
double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
unsigned int dummy_latency_index = 0;
@@ -475,8 +477,8 @@ void dcn30_fpu_calculate_wm_and_dlg(
/* Make set D = set A until set D is enabled */
context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
- if (!context->res_ctx.pipe_ctx[i].stream)
+ for (pipe_i = 0, pipe_idx = 0; pipe_i < dc->res_pool->pipe_count; pipe_i++) {
+ if (!context->res_ctx.pipe_ctx[pipe_i].stream)
continue;
pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
@@ -500,9 +502,9 @@ void dcn30_fpu_calculate_wm_and_dlg(
context->bw_ctx.dml.vba.DRAMSpeed <= 1700 &&
context->bw_ctx.dml.vba.DRAMSpeed >= 1500) {
- for (i = 0; i < dc->dml.soc.num_states; i++) {
- if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) {
- context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts;
+ for (state_i = 0; state_i < dc->dml.soc.num_states; state_i++) {
+ if (dc->dml.soc.clock_limits[state_i].dram_speed_mts > 1700) {
+ context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[state_i].dram_speed_mts;
break;
}
}
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -366,7 +366,7 @@ static void CalculatePixelDeliveryTimes(
double CursorRequestDeliveryTimePrefetch[]);
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
@@ -439,7 +439,7 @@ static void CalculateVMGroupAndRequestTi
double TimePerVMRequestFlip[]);
static void CalculateStutterEfficiency(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
long ROBBufferSizeInKByte,
double TotalDataReadBandwidth,
double DCFCLK,
@@ -479,7 +479,7 @@ static void CalculateStutterEfficiency(
static void CalculateSwathAndDETConfiguration(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
unsigned int DETBufferSizeInKByte,
double MaximumSwathWidthLuma[],
double MaximumSwathWidthChroma[],
@@ -518,7 +518,7 @@ static void CalculateSwathAndDETConfigur
bool *ViewportSizeSupport);
static void CalculateSwathWidth(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
unsigned int ViewportWidth[],
@@ -572,7 +572,7 @@ static double CalculateExtraLatencyBytes
int MetaChunkSize,
bool GPUVMEnable,
bool HostVMEnable,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
int NumberOfDPP[],
int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
@@ -1335,11 +1335,12 @@ static void CalculateDCCConfiguration(
max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
eff_surf_width_l =
- (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma);
+ (SurfaceWidthLuma > (unsigned long)max_vp_horz_width ?
+ (unsigned long)max_vp_horz_width : SurfaceWidthLuma);
eff_surf_width_c = eff_surf_width_l / (1 + yuv420);
eff_surf_height_l = (
- SurfaceHeightLuma > max_vp_vert_height ?
- max_vp_vert_height : SurfaceHeightLuma);
+ SurfaceHeightLuma > (unsigned long)max_vp_vert_height ?
+ (unsigned long)max_vp_vert_height : SurfaceHeightLuma);
eff_surf_height_c = eff_surf_height_l / (1 + yuv420);
full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY;
@@ -3381,8 +3382,8 @@ void dml30_ModeSupportAndSystemConfigura
{
struct vba_vars_st *v = &mode_lib->vba;
int MinPrefetchMode, MaxPrefetchMode;
- int i, start_state;
- unsigned int j, k, m;
+ int idx, start_state;
+ unsigned int i, j, k, m;
bool EnoughWritebackUnits = true;
bool WritebackModeSupport = true;
bool ViewportExceedsSurface = false;
@@ -4913,33 +4914,39 @@ void dml30_ModeSupportAndSystemConfigura
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = v->soc.num_states - 1; i >= start_state; i--) {
+ for (idx = v->soc.num_states - 1; idx >= start_state; idx--) {
for (j = 0; j < 2; j++) {
- if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
- && v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
- && v->NotEnoughDSCUnits[i] == 0
- && v->DTBCLKRequiredMoreThanSupported[i] == 0
- && v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1
+ if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1
+ && v->ViewportSizeSupport[idx][j] == 1
+ && v->DIOSupport[idx] == 1 && v->ODMCombine4To1SupportCheckOK[idx] == 1
+ && v->NotEnoughDSCUnits[idx] == 0
+ && v->DTBCLKRequiredMoreThanSupported[idx] == 0
+ && v->ROBSupport[idx][j] == 1 && v->DISPCLK_DPPCLK_Support[idx][j] == 1
+ && v->TotalAvailablePipesSupport[idx][j] == 1
&& EnoughWritebackUnits == 1 && WritebackModeSupport == 1
- && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1 && v->CursorSupport == 1 && v->PitchSupport == 1
- && ViewportExceedsSurface == 0 && v->PrefetchSupported[i][j] == 1 && v->DynamicMetadataSupported[i][j] == 1
- && v->TotalVerticalActiveBandwidthSupport[i][j] == 1 && v->VRatioInPrefetchSupported[i][j] == 1
- && v->PTEBufferSizeNotExceeded[i][j] == 1 && v->NonsupportedDSCInputBPC == 0
+ && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1
+ && v->CursorSupport == 1 && v->PitchSupport == 1
+ && ViewportExceedsSurface == 0 && v->PrefetchSupported[idx][j] == 1
+ && v->DynamicMetadataSupported[idx][j] == 1
+ && v->TotalVerticalActiveBandwidthSupport[idx][j] == 1
+ && v->VRatioInPrefetchSupported[idx][j] == 1
+ && v->PTEBufferSizeNotExceeded[idx][j] == 1 && v->NonsupportedDSCInputBPC == 0
&& ((v->HostVMEnable == 0 && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true)) {
- v->ModeSupport[i][j] = true;
+ || v->ImmediateFlipSupportedForState[idx][j] == true)) {
+ v->ModeSupport[idx][j] = true;
} else {
- v->ModeSupport[i][j] = false;
+ v->ModeSupport[idx][j] = false;
}
}
}
{
unsigned int MaximumMPCCombine = 0;
- for (i = v->soc.num_states; i >= start_state; i--) {
- if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
- v->VoltageLevel = i;
- v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
- if (v->ModeSupport[i][1] == true) {
+ for (idx = v->soc.num_states; idx >= start_state; idx--) {
+ if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true
+ || v->ModeSupport[idx][1] == true) {
+ v->VoltageLevel = idx;
+ v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true;
+ if (v->ModeSupport[idx][1] == true) {
MaximumMPCCombine = 1;
} else {
MaximumMPCCombine = 0;
@@ -5400,7 +5407,7 @@ static void CalculatePixelDeliveryTimes(
}
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
@@ -5686,7 +5693,7 @@ static void CalculateVMGroupAndRequestTi
}
static void CalculateStutterEfficiency(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
long ROBBufferSizeInKByte,
double TotalDataReadBandwidth,
double DCFCLK,
@@ -5840,7 +5847,7 @@ static void CalculateStutterEfficiency(
static void CalculateSwathAndDETConfiguration(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
unsigned int DETBufferSizeInKByte,
double MaximumSwathWidthLuma[],
double MaximumSwathWidthChroma[],
@@ -5891,7 +5898,7 @@ static void CalculateSwathAndDETConfigur
long RoundedUpSwathSizeBytesC = 0;
double SwathWidthSingleDPP[DC__NUM_DPP__MAX] = { 0 };
double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX] = { 0 };
- int k;
+ unsigned int k;
CalculateSwathWidth(
ForceSingleDPP,
@@ -5980,21 +5987,21 @@ static void CalculateSwathAndDETConfigur
}
if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
- <= DETBufferSizeInKByte * 1024 / 2) {
+ <= (long)DETBufferSizeInKByte * 1024 / 2) {
SwathHeightY[k] = MaximumSwathHeightY[k];
SwathHeightC[k] = MaximumSwathHeightC[k];
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
} else if (RoundedUpMaxSwathSizeBytesY >= 1.5 * RoundedUpMaxSwathSizeBytesC
&& RoundedUpMinSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
- <= DETBufferSizeInKByte * 1024 / 2) {
+ <= (long)DETBufferSizeInKByte * 1024 / 2) {
SwathHeightY[k] = MinimumSwathHeightY;
SwathHeightC[k] = MaximumSwathHeightC[k];
RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY;
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
} else if (RoundedUpMaxSwathSizeBytesY < 1.5 * RoundedUpMaxSwathSizeBytesC
&& RoundedUpMaxSwathSizeBytesY + RoundedUpMinSwathSizeBytesC
- <= DETBufferSizeInKByte * 1024 / 2) {
+ <= (long)DETBufferSizeInKByte * 1024 / 2) {
SwathHeightY[k] = MaximumSwathHeightY[k];
SwathHeightC[k] = MinimumSwathHeightC;
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
@@ -6018,7 +6025,7 @@ static void CalculateSwathAndDETConfigur
}
if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC
- > DETBufferSizeInKByte * 1024 / 2
+ > (long)DETBufferSizeInKByte * 1024 / 2
|| SwathWidth[k] > MaximumSwathWidthLuma[k]
|| (SwathHeightC[k] > 0
&& SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
@@ -6032,7 +6039,7 @@ static void CalculateSwathAndDETConfigur
static void CalculateSwathWidth(
bool ForceSingleDPP,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
unsigned int ViewportWidth[],
@@ -6185,7 +6192,7 @@ static double CalculateExtraLatencyBytes
int MetaChunkSize,
bool GPUVMEnable,
bool HostVMEnable,
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
int NumberOfDPP[],
int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -326,7 +326,8 @@ void dcn301_fpu_update_bw_bounding_box(s
struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
struct clk_limit_table *clk_table = &bw_params->clk_table;
unsigned int i, closest_clk_lvl;
- int j = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ int j = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
@@ -429,7 +430,7 @@ void dcn301_fpu_calculate_wm_and_dlg(str
int pipe_cnt,
int vlevel_req)
{
- int i, pipe_idx;
+ unsigned int i, pipe_idx;
int vlevel, vlevel_max;
struct wm_range_table_entry *table_entry;
struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
@@ -218,7 +218,7 @@ void dcn302_fpu_update_bw_bounding_box(s
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
if (bw_params->clk_table.entries[0].memclk_mhz) {
- int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+ unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
@@ -214,7 +214,7 @@ void dcn303_fpu_update_bw_bounding_box(s
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
if (bw_params->clk_table.entries[0].memclk_mhz) {
- int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+ unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -485,9 +485,12 @@ void dcn31_calculate_wm_and_dlg_fp(
int pipe_cnt,
int vlevel)
{
- int i, pipe_idx, total_det = 0, active_hubp_count = 0;
+ int total_det = 0, active_hubp_count = 0;
+ unsigned int i, pipe_idx;
double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
uint32_t cstate_enter_plus_exit_z8_ns;
+ uint32_t minimum_z8_residency_time_ns =
+ (uint32_t)dc->debug.minimum_z8_residency_time * 1000U;
dc_assert_fp_enabled();
@@ -511,8 +514,8 @@ void dcn31_calculate_wm_and_dlg_fp(
get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time &&
- cstate_enter_plus_exit_z8_ns < dc->debug.minimum_z8_residency_time * 1000)
- cstate_enter_plus_exit_z8_ns = dc->debug.minimum_z8_residency_time * 1000;
+ cstate_enter_plus_exit_z8_ns < minimum_z8_residency_time_ns)
+ cstate_enter_plus_exit_z8_ns = minimum_z8_residency_time_ns;
/* Set A:
* All clocks min required
@@ -592,7 +595,7 @@ void dcn31_update_bw_bounding_box_fpu(st
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
struct clk_limit_table *clk_table = &bw_params->clk_table;
unsigned int i, closest_clk_lvl;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
dc_assert_fp_enabled();
@@ -668,7 +671,7 @@ void dcn31_update_bw_bounding_box_fpu(st
void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
{
struct clk_limit_table *clk_table = &bw_params->clk_table;
- int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
@@ -731,7 +734,7 @@ void dcn316_update_bw_bounding_box_fpu(s
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
struct clk_limit_table *clk_table = &bw_params->clk_table;
unsigned int i, closest_clk_lvl;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
dc_assert_fp_enabled();
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -1510,10 +1510,10 @@ static void CalculateDCCConfiguration(
double detile_buf_vp_horz_limit;
double detile_buf_vp_vert_limit;
- int MAS_vp_horz_limit;
- int MAS_vp_vert_limit;
- int max_vp_horz_width;
- int max_vp_vert_height;
+ unsigned int MAS_vp_horz_limit;
+ unsigned int MAS_vp_vert_limit;
+ unsigned int max_vp_horz_width;
+ unsigned int max_vp_vert_height;
int eff_surf_width_l;
int eff_surf_width_c;
int eff_surf_height_l;
@@ -3785,7 +3785,8 @@ static noinline void CalculatePrefetchSc
static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[])
{
- int i, total_pipes = 0;
+ int total_pipes = 0;
+ unsigned int i;
for (i = 0; i < NumberOfActivePlanes; i++)
total_pipes += NoOfDPPThisState[i];
DETBufferSizeInKByte[0] = ((config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB) / 64 / total_pipes) * 64;
@@ -3800,8 +3801,8 @@ void dml31_ModeSupportAndSystemConfigura
{
struct vba_vars_st *v = &mode_lib->vba;
- int i, j;
- unsigned int k, m;
+ int idx;
+ unsigned int i, j, k, m;
int ReorderingBytes;
int MinPrefetchMode = 0, MaxPrefetchMode = 2;
bool NoChroma = true;
@@ -5451,46 +5452,53 @@ void dml31_ModeSupportAndSystemConfigura
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = v->soc.num_states - 1; i >= 0; i--) {
+ for (idx = (int)v->soc.num_states - 1; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
- if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
- && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
- && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
- && v->DTBCLKRequiredMoreThanSupported[i] == false
- && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
- && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
+ if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true
+ && v->ViewportSizeSupport[idx][j] == true
+ && v->LinkCapacitySupport[idx] == true && !P2IWith420
+ && !DSCOnlyIfNecessaryWithBPP
+ && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true
+ && v->NotEnoughDSCUnits[idx] == false
+ && v->DTBCLKRequiredMoreThanSupported[idx] == false
+ && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true
+ && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true
&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
- && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
- && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
- && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
- && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
+ && v->CursorSupport == true && v->PitchSupport == true
+ && ViewportExceedsSurface == false
+ && v->PrefetchSupported[idx][j] == true
+ && v->DynamicMetadataSupported[idx][j] == true
+ && v->TotalVerticalActiveBandwidthSupport[idx][j] == true
+ && v->VRatioInPrefetchSupported[idx][j] == true
+ && v->PTEBufferSizeNotExceeded[idx][j] == true
+ && v->NonsupportedDSCInputBPC == false
&& ((v->HostVMEnable == false
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true)
+ || v->ImmediateFlipSupportedForState[idx][j] == true)
&& FMTBufferExceeded == false) {
- v->ModeSupport[i][j] = true;
+ v->ModeSupport[idx][j] = true;
} else {
- v->ModeSupport[i][j] = false;
+ v->ModeSupport[idx][j] = false;
#ifdef __DML_VBA_DEBUG__
if (v->ScaleRatioAndTapsSupport == false)
dml_print("DML SUPPORT: ScaleRatioAndTapsSupport failed");
if (v->SourceFormatPixelAndScanSupport == false)
dml_print("DML SUPPORT: SourceFormatPixelAndScanSupport failed");
- if (v->ViewportSizeSupport[i][j] == false)
+ if (v->ViewportSizeSupport[idx][j] == false)
dml_print("DML SUPPORT: ViewportSizeSupport failed");
- if (v->LinkCapacitySupport[i] == false)
+ if (v->LinkCapacitySupport[idx] == false)
dml_print("DML SUPPORT: LinkCapacitySupport failed");
- if (v->ODMCombine4To1SupportCheckOK[i] == false)
+ if (v->ODMCombine4To1SupportCheckOK[idx] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
- if (v->NotEnoughDSCUnits[i] == true)
+ if (v->NotEnoughDSCUnits[idx] == true)
dml_print("DML SUPPORT: NotEnoughDSCUnits");
- if (v->DTBCLKRequiredMoreThanSupported[i] == true)
+ if (v->DTBCLKRequiredMoreThanSupported[idx] == true)
dml_print("DML SUPPORT: DTBCLKRequiredMoreThanSupported");
- if (v->ROBSupport[i][j] == false)
+ if (v->ROBSupport[idx][j] == false)
dml_print("DML SUPPORT: ROBSupport failed");
- if (v->DISPCLK_DPPCLK_Support[i][j] == false)
+ if (v->DISPCLK_DPPCLK_Support[idx][j] == false)
dml_print("DML SUPPORT: DISPCLK_DPPCLK_Support failed");
- if (v->TotalAvailablePipesSupport[i][j] == false)
+ if (v->TotalAvailablePipesSupport[idx][j] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
if (EnoughWritebackUnits == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
@@ -5504,21 +5512,21 @@ void dml31_ModeSupportAndSystemConfigura
dml_print("DML SUPPORT: PitchSupport failed");
if (ViewportExceedsSurface == true)
dml_print("DML SUPPORT: ViewportExceedsSurface failed");
- if (v->PrefetchSupported[i][j] == false)
+ if (v->PrefetchSupported[idx][j] == false)
dml_print("DML SUPPORT: PrefetchSupported failed");
- if (v->DynamicMetadataSupported[i][j] == false)
+ if (v->DynamicMetadataSupported[idx][j] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
- if (v->TotalVerticalActiveBandwidthSupport[i][j] == false)
+ if (v->TotalVerticalActiveBandwidthSupport[idx][j] == false)
dml_print("DML SUPPORT: TotalVerticalActiveBandwidthSupport failed");
- if (v->VRatioInPrefetchSupported[i][j] == false)
+ if (v->VRatioInPrefetchSupported[idx][j] == false)
dml_print("DML SUPPORT: VRatioInPrefetchSupported failed");
- if (v->PTEBufferSizeNotExceeded[i][j] == false)
+ if (v->PTEBufferSizeNotExceeded[idx][j] == false)
dml_print("DML SUPPORT: PTEBufferSizeNotExceeded failed");
if (v->NonsupportedDSCInputBPC == true)
dml_print("DML SUPPORT: NonsupportedDSCInputBPC failed");
if (!((v->HostVMEnable == false
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true))
+ || v->ImmediateFlipSupportedForState[idx][j] == true))
dml_print("DML SUPPORT: ImmediateFlipRequirement failed");
if (FMTBufferExceeded == true)
dml_print("DML SUPPORT: FMTBufferExceeded failed");
@@ -5529,11 +5537,12 @@ void dml31_ModeSupportAndSystemConfigura
{
unsigned int MaximumMPCCombine = 0;
- for (i = v->soc.num_states; i >= 0; i--) {
- if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
- v->VoltageLevel = i;
- v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
- if (v->ModeSupport[i][0] == true) {
+ for (idx = (int)v->soc.num_states; idx >= 0; idx--) {
+ if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true
+ || v->ModeSupport[idx][1] == true) {
+ v->VoltageLevel = idx;
+ v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true;
+ if (v->ModeSupport[idx][0] == true) {
MaximumMPCCombine = 0;
} else {
MaximumMPCCombine = 1;
@@ -5541,7 +5550,7 @@ void dml31_ModeSupportAndSystemConfigura
}
}
v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
- for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
+ for (k = 0; k < v->NumberOfActivePlanes; k++) {
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
}
@@ -5599,7 +5608,7 @@ static void CalculateWatermarksAndDRAMSp
double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
double WritebackDRAMClockChangeLatencyHiding;
double TotalPixelBW = 0.0;
- int k, j;
+ unsigned int k, j;
v->UrgentWatermark = UrgentLatency + ExtraLatency;
@@ -5787,7 +5796,7 @@ static void CalculateDCFCLKDeepSleep(
double DisplayPipeLineDeliveryTimeLuma;
double DisplayPipeLineDeliveryTimeChroma;
double ReadBandwidth = 0.0;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
@@ -5938,7 +5947,7 @@ static void CalculatePixelDeliveryTimes(
double CursorRequestDeliveryTimePrefetch[])
{
double req_per_swath_ub;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (VRatio[k] <= 1) {
@@ -6235,7 +6244,7 @@ static void CalculateVMGroupAndRequestTi
(void)dpte_row_width_chroma_ub;
int num_group_per_lower_vm_stage;
int num_req_per_lower_vm_stage;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
@@ -6676,12 +6685,12 @@ static void CalculateSwathAndDETConfigur
int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int MinimumSwathHeightC;
- int RoundedUpMaxSwathSizeBytesY;
- int RoundedUpMaxSwathSizeBytesC;
- int RoundedUpMinSwathSizeBytesY;
- int RoundedUpMinSwathSizeBytesC;
- int RoundedUpSwathSizeBytesY;
- int RoundedUpSwathSizeBytesC;
+ unsigned int RoundedUpMaxSwathSizeBytesY;
+ unsigned int RoundedUpMaxSwathSizeBytesC;
+ unsigned int RoundedUpMinSwathSizeBytesY;
+ unsigned int RoundedUpMinSwathSizeBytesC;
+ unsigned int RoundedUpSwathSizeBytesY;
+ unsigned int RoundedUpSwathSizeBytesC;
double SwathWidthSingleDPP[DC__NUM_DPP__MAX];
double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX];
int k;
@@ -7052,7 +7061,9 @@ static noinline_for_stack void UseMinimu
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1, i, j, k;
+ int dummy1;
+ unsigned int j, k;
+ unsigned int i;
double NormalEfficiency, dummy2, dummy3;
double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
@@ -7079,9 +7090,8 @@ static noinline_for_stack void UseMinimu
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
}
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
- }
MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j];
@@ -7182,9 +7192,8 @@ static noinline_for_stack void UseMinimu
}
}
DCFCLKRequiredForPeakBandwidth = 0;
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
- }
MinimumTvmPlus2Tr0 = v->UrgLatency[i]
* (v->GPUVMEnable == true ?
(v->HostVMEnable == true ?
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -185,7 +185,7 @@ void dcn314_update_bw_bounding_box_fpu(s
struct _vcs_dpi_voltage_scaling_st *clock_limits =
dcn3_14_soc.clock_limits;
unsigned int i, closest_clk_lvl;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
dc_assert_fp_enabled();
@@ -308,7 +308,8 @@ int dcn314_populate_dml_pipes_from_conte
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ int pipe_cnt;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -407,7 +407,7 @@ static void CalculatePixelDeliveryTimes(
double CursorRequestDeliveryTimePrefetch[]);
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
@@ -1527,14 +1527,14 @@ static void CalculateDCCConfiguration(
double detile_buf_vp_horz_limit;
double detile_buf_vp_vert_limit;
- int MAS_vp_horz_limit;
- int MAS_vp_vert_limit;
- int max_vp_horz_width;
- int max_vp_vert_height;
- int eff_surf_width_l;
- int eff_surf_width_c;
- int eff_surf_height_l;
- int eff_surf_height_c;
+ unsigned int MAS_vp_horz_limit;
+ unsigned int MAS_vp_vert_limit;
+ unsigned int max_vp_horz_width;
+ unsigned int max_vp_vert_height;
+ unsigned int eff_surf_width_l;
+ unsigned int eff_surf_width_c;
+ unsigned int eff_surf_height_l;
+ unsigned int eff_surf_height_c;
int full_swath_bytes_horz_wc_l;
int full_swath_bytes_horz_wc_c;
@@ -3893,7 +3893,8 @@ void dml314_ModeSupportAndSystemConfigur
{
struct vba_vars_st *v = &mode_lib->vba;
- int i, j;
+ int j;
+ unsigned int i;
unsigned int k, m;
int ReorderingBytes;
int MinPrefetchMode = 0, MaxPrefetchMode = 2;
@@ -5537,30 +5538,37 @@ void dml314_ModeSupportAndSystemConfigur
}
/*Mode Support, Voltage State and SOC Configuration*/
- for (i = v->soc.num_states - 1; i >= 0; i--) {
+ for (int idx = (int)v->soc.num_states - 1; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
- if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
- && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
- && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
- && v->DTBCLKRequiredMoreThanSupported[i] == false
- && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
- && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
+ if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true
+ && v->ViewportSizeSupport[idx][j] == true
+ && v->LinkCapacitySupport[idx] == true && !P2IWith420
+ && !DSCOnlyIfNecessaryWithBPP
+ && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true
+ && v->NotEnoughDSCUnits[idx] == false
+ && v->DTBCLKRequiredMoreThanSupported[idx] == false
+ && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true
+ && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true
&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
- && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
- && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
- && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
- && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
+ && v->CursorSupport == true && v->PitchSupport == true
+ && ViewportExceedsSurface == false
+ && v->PrefetchSupported[idx][j] == true
+ && v->DynamicMetadataSupported[idx][j] == true
+ && v->TotalVerticalActiveBandwidthSupport[idx][j] == true
+ && v->VRatioInPrefetchSupported[idx][j] == true
+ && v->PTEBufferSizeNotExceeded[idx][j] == true
+ && v->NonsupportedDSCInputBPC == false
&& ((v->HostVMEnable == false
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
- || v->ImmediateFlipSupportedForState[i][j] == true)
+ || v->ImmediateFlipSupportedForState[idx][j] == true)
&& FMTBufferExceeded == false) {
- v->ModeSupport[i][j] = true;
+ v->ModeSupport[idx][j] = true;
} else {
- v->ModeSupport[i][j] = false;
+ v->ModeSupport[idx][j] = false;
}
}
}
- for (i = v->soc.num_states; i >= 0; i--) {
+ for (int idx = (int)v->soc.num_states; idx >= 0; idx--) {
for (j = 0; j < 2; j++) {
enum dm_validation_status status = DML_VALIDATION_OK;
@@ -5568,7 +5576,7 @@ void dml314_ModeSupportAndSystemConfigur
status = DML_FAIL_SCALE_RATIO_TAP;
} else if (!v->SourceFormatPixelAndScanSupport) {
status = DML_FAIL_SOURCE_PIXEL_FORMAT;
- } else if (!v->ViewportSizeSupport[i][j]) {
+ } else if (!v->ViewportSizeSupport[idx][j]) {
status = DML_FAIL_VIEWPORT_SIZE;
} else if (P2IWith420) {
status = DML_FAIL_P2I_WITH_420;
@@ -5576,15 +5584,15 @@ void dml314_ModeSupportAndSystemConfigur
status = DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP;
} else if (DSC422NativeNotSupported) {
status = DML_FAIL_NOT_DSC422_NATIVE;
- } else if (!v->ODMCombine4To1SupportCheckOK[i]) {
+ } else if (!v->ODMCombine4To1SupportCheckOK[idx]) {
status = DML_FAIL_ODM_COMBINE4TO1;
- } else if (v->NotEnoughDSCUnits[i]) {
+ } else if (v->NotEnoughDSCUnits[idx]) {
status = DML_FAIL_NOT_ENOUGH_DSC;
- } else if (!v->ROBSupport[i][j]) {
+ } else if (!v->ROBSupport[idx][j]) {
status = DML_FAIL_REORDERING_BUFFER;
- } else if (!v->DISPCLK_DPPCLK_Support[i][j]) {
+ } else if (!v->DISPCLK_DPPCLK_Support[idx][j]) {
status = DML_FAIL_DISPCLK_DPPCLK;
- } else if (!v->TotalAvailablePipesSupport[i][j]) {
+ } else if (!v->TotalAvailablePipesSupport[idx][j]) {
status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
} else if (!EnoughWritebackUnits) {
status = DML_FAIL_ENOUGH_WRITEBACK_UNITS;
@@ -5598,36 +5606,36 @@ void dml314_ModeSupportAndSystemConfigur
status = DML_FAIL_PITCH_SUPPORT;
} else if (ViewportExceedsSurface) {
status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE;
- } else if (!v->PrefetchSupported[i][j]) {
+ } else if (!v->PrefetchSupported[idx][j]) {
status = DML_FAIL_PREFETCH_SUPPORT;
- } else if (!v->DynamicMetadataSupported[i][j]) {
+ } else if (!v->DynamicMetadataSupported[idx][j]) {
status = DML_FAIL_DYNAMIC_METADATA;
- } else if (!v->TotalVerticalActiveBandwidthSupport[i][j]) {
+ } else if (!v->TotalVerticalActiveBandwidthSupport[idx][j]) {
status = DML_FAIL_TOTAL_V_ACTIVE_BW;
- } else if (!v->VRatioInPrefetchSupported[i][j]) {
+ } else if (!v->VRatioInPrefetchSupported[idx][j]) {
status = DML_FAIL_V_RATIO_PREFETCH;
- } else if (!v->PTEBufferSizeNotExceeded[i][j]) {
+ } else if (!v->PTEBufferSizeNotExceeded[idx][j]) {
status = DML_FAIL_PTE_BUFFER_SIZE;
} else if (v->NonsupportedDSCInputBPC) {
status = DML_FAIL_DSC_INPUT_BPC;
} else if ((v->HostVMEnable
- && !v->ImmediateFlipSupportedForState[i][j])) {
+ && !v->ImmediateFlipSupportedForState[idx][j])) {
status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
} else if (FMTBufferExceeded) {
status = DML_FAIL_FMT_BUFFER_EXCEEDED;
}
- mode_lib->vba.ValidationStatus[i] = status;
+ mode_lib->vba.ValidationStatus[idx] = status;
}
}
{
unsigned int MaximumMPCCombine = 0;
-
- for (i = v->soc.num_states; i >= 0; i--) {
- if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
- v->VoltageLevel = i;
- v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
- if (v->ModeSupport[i][0] == true) {
+ for (int idx = (int)v->soc.num_states; idx >= 0; idx--) {
+ if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true
+ || v->ModeSupport[idx][1] == true) {
+ v->VoltageLevel = idx;
+ v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true;
+ if (v->ModeSupport[idx][0] == true) {
MaximumMPCCombine = 0;
} else {
MaximumMPCCombine = 1;
@@ -5635,7 +5643,7 @@ void dml314_ModeSupportAndSystemConfigur
}
}
v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
- for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
+ for (k = 0; k < v->NumberOfActivePlanes; k++) {
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
}
@@ -5693,7 +5701,7 @@ static void CalculateWatermarksAndDRAMSp
double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
double WritebackDRAMClockChangeLatencyHiding;
double TotalPixelBW = 0.0;
- int k, j;
+ unsigned int k, j;
v->UrgentWatermark = UrgentLatency + ExtraLatency;
@@ -5881,7 +5889,7 @@ static void CalculateDCFCLKDeepSleep(
double DisplayPipeLineDeliveryTimeLuma;
double DisplayPipeLineDeliveryTimeChroma;
double ReadBandwidth = 0.0;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
@@ -6032,7 +6040,7 @@ static void CalculatePixelDeliveryTimes(
double CursorRequestDeliveryTimePrefetch[])
{
double req_per_swath_ub;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (VRatio[k] <= 1) {
@@ -6132,7 +6140,7 @@ static void CalculatePixelDeliveryTimes(
}
static void CalculateMetaAndPTETimes(
- int NumberOfActivePlanes,
+ unsigned int NumberOfActivePlanes,
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
@@ -6198,7 +6206,7 @@ static void CalculateMetaAndPTETimes(
unsigned int dpte_groups_per_row_luma_ub;
unsigned int dpte_group_width_chroma;
unsigned int dpte_groups_per_row_chroma_ub;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
@@ -6330,7 +6338,7 @@ static void CalculateVMGroupAndRequestTi
(void)dpte_row_width_chroma_ub;
int num_group_per_lower_vm_stage;
int num_req_per_lower_vm_stage;
- int k;
+ unsigned int k;
for (k = 0; k < NumberOfActivePlanes; ++k) {
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
@@ -6770,12 +6778,12 @@ static void CalculateSwathAndDETConfigur
int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int MinimumSwathHeightC;
- int RoundedUpMaxSwathSizeBytesY;
- int RoundedUpMaxSwathSizeBytesC;
- int RoundedUpMinSwathSizeBytesY;
- int RoundedUpMinSwathSizeBytesC;
- int RoundedUpSwathSizeBytesY;
- int RoundedUpSwathSizeBytesC;
+ unsigned int RoundedUpMaxSwathSizeBytesY;
+ unsigned int RoundedUpMaxSwathSizeBytesC;
+ unsigned int RoundedUpMinSwathSizeBytesY;
+ unsigned int RoundedUpMinSwathSizeBytesC;
+ unsigned int RoundedUpSwathSizeBytesY;
+ unsigned int RoundedUpSwathSizeBytesC;
double SwathWidthSingleDPP[DC__NUM_DPP__MAX];
double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX];
int k;
@@ -7139,7 +7147,8 @@ static noinline_for_stack void UseMinimu
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1, i, j, k;
+ int dummy1, j;
+ unsigned int i, k;
double NormalEfficiency, dummy2, dummy3;
double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
@@ -7166,7 +7175,7 @@ static noinline_for_stack void UseMinimu
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
}
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
@@ -7269,7 +7278,7 @@ static noinline_for_stack void UseMinimu
}
}
DCFCLKRequiredForPeakBandwidth = 0;
- for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
+ for (k = 0; k < v->NumberOfActivePlanes; ++k)
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
MinimumTvmPlus2Tr0 = v->UrgLatency[i]
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -297,7 +297,7 @@ int dcn32_find_dummy_latency_index_for_f
dcn32_subvp_in_use(dc, context))
vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
- if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
+ if (vlevel < (int)context->bw_ctx.dml.vba.soc.num_states &&
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
break;
@@ -418,8 +418,8 @@ static void insert_entry_into_table_sort
unsigned int *num_entries,
struct _vcs_dpi_voltage_scaling_st *entry)
{
- int i = 0;
- int index = 0;
+ unsigned int i = 0;
+ unsigned int index = 0;
dc_assert_fp_enabled();
@@ -773,8 +773,8 @@ static bool subvp_subvp_schedulable(stru
subvp_pipes[1]->stream->timing.h_total) /
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
- if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
- (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
+ if ((vactive1_us - vblank2_us) / 2 > (int32_t)max_microschedule_us &&
+ (vactive2_us - vblank1_us) / 2 > (int32_t)max_microschedule_us)
return true;
return false;
@@ -1013,8 +1013,8 @@ static bool subvp_subvp_admissable(struc
}
if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
- (min_refresh >= subvp_high_refresh_list.min_refresh &&
- max_refresh <= subvp_high_refresh_list.max_refresh)))
+ (min_refresh >= (uint32_t)subvp_high_refresh_list.min_refresh &&
+ max_refresh <= (uint32_t)subvp_high_refresh_list.max_refresh)))
result = true;
return result;
@@ -1092,7 +1092,7 @@ static bool subvp_validate_static_schedu
static void assign_subvp_index(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
int index = 0;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1224,7 +1224,8 @@ static bool update_pipe_slice_table_with
*/
struct pipe_ctx *pipe;
bool odm;
- int dc_pipe_idx, dml_pipe_idx = 0;
+ unsigned int dc_pipe_idx;
+ int dml_pipe_idx = 0;
bool updated = false;
for (dc_pipe_idx = 0;
@@ -1466,7 +1467,7 @@ static bool dcn32_full_validate_bw_helpe
*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states) {
+ if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) {
*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
vba->VoltageLevel = *vlevel;
}
@@ -1527,14 +1528,14 @@ static bool dcn32_full_validate_bw_helpe
/* Check that vlevel requested supports pstate or not
* if not, select the lowest vlevel that supports it
*/
- for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
+ for (i = *vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) {
if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) {
*vlevel = i;
break;
}
}
- if (*vlevel < context->bw_ctx.dml.soc.num_states
+ if (*vlevel < (int)context->bw_ctx.dml.soc.num_states
&& subvp_validate_static_schedulability(dc, context, *vlevel))
found_supported_config = true;
if (found_supported_config) {
@@ -1566,7 +1567,7 @@ static bool dcn32_full_validate_bw_helpe
*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states) {
+ if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) {
*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
vba->VoltageLevel = *vlevel;
}
@@ -1599,7 +1600,7 @@ static bool dcn32_full_validate_bw_helpe
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
@@ -1614,7 +1615,8 @@ static void dcn32_calculate_dlg_params(s
display_e2e_pipe_params_st *pipes,
int pipe_cnt, int vlevel)
{
- int i, pipe_idx, active_hubp_count = 0;
+ int pipe_idx, active_hubp_count = 0;
+ unsigned int i;
bool usr_retraining_support = false;
bool unbounded_req_enabled = false;
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
@@ -1650,8 +1652,8 @@ static void dcn32_calculate_dlg_params(s
usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
ASSERT(usr_retraining_support);
- if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
- context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
+ if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
+ context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz;
unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
@@ -1904,7 +1906,8 @@ static bool dcn32_apply_merge_split_flag
int *split,
bool *merge)
{
- int i, pipe_idx;
+ int pipe_idx;
+ unsigned int i;
bool newly_split[MAX_PIPES] = { false };
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
@@ -2165,7 +2168,7 @@ bool dcn32_internal_validate_bw(struct d
context->bw_ctx.dml.validate_max_state = false;
- if (vlevel < context->bw_ctx.dml.soc.num_states) {
+ if (vlevel < (int)context->bw_ctx.dml.soc.num_states) {
memset(split, 0, sizeof(split));
memset(merge, 0, sizeof(merge));
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
@@ -2179,7 +2182,7 @@ bool dcn32_internal_validate_bw(struct d
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ for (i = 0, pipe_idx = 0; i < (int)dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
@@ -2233,7 +2236,7 @@ bool dcn32_internal_validate_bw(struct d
flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {
/* check the context constructed with pipe split flags is still valid*/
bool flags_valid = false;
- for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
+ for (i = flag_vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) {
if (vba->ModeSupport[i][flag_max_mpc_comb]) {
vba->maxMpcComb = flag_max_mpc_comb;
vba->VoltageLevel = i;
@@ -2267,7 +2270,8 @@ void dcn32_calculate_wm_and_dlg_fpu(stru
int pipe_cnt,
int vlevel)
{
- int i, pipe_idx, vlevel_temp = 0;
+ int pipe_idx, vlevel_temp = 0;
+ unsigned int i;
double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed;
@@ -2619,7 +2623,7 @@ static void dcn32_get_optimal_dcfclk_fcl
static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
unsigned int index)
{
- int i;
+ unsigned int i;
if (*num_entries == 0)
return;
@@ -2686,7 +2690,7 @@ static void sort_entries_with_same_bw(st
unsigned int end_index = 0;
unsigned int current_bw = 0;
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i < (*num_entries - 1); i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
current_bw = table[i].net_bw_in_kbytes_sec;
start_index = i;
@@ -2697,8 +2701,8 @@ static void sort_entries_with_same_bw(st
}
if (start_index != end_index) {
- for (int j = start_index; j < end_index; j++) {
- for (int k = start_index; k < end_index; k++) {
+ for (unsigned int j = start_index; j < end_index; j++) {
+ for (unsigned int k = start_index; k < end_index; k++) {
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
swap_table_entries(&table[k], &table[k+1]);
}
@@ -2717,7 +2721,7 @@ static void sort_entries_with_same_bw(st
*/
static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i < (*num_entries - 1); i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
(table[i].fabricclk_mhz > table[i+1].fabricclk_mhz))
@@ -2765,7 +2769,8 @@ static int override_max_clk_values(struc
static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- int i, j;
+ int i;
+ unsigned int j;
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
@@ -2852,8 +2857,8 @@ static int build_synthetic_soc_states(bo
entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
// Insert all the DCFCLK STAs
- for (i = 0; i < num_dcfclk_stas; i++) {
- entry.dcfclk_mhz = dcfclk_sta_targets[i];
+ for (j = 0; j < num_dcfclk_stas; j++) {
+ entry.dcfclk_mhz = dcfclk_sta_targets[j];
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
@@ -2872,10 +2877,10 @@ static int build_synthetic_soc_states(bo
insert_entry_into_table_sorted(table, num_entries, &entry);
// Insert the UCLK DPMS
- for (i = 0; i < num_uclk_dpms; i++) {
+ for (j = 0; j < num_uclk_dpms; j++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = 0;
- entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
+ entry.dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
get_optimal_ntuple(&entry);
entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
@@ -2884,9 +2889,9 @@ static int build_synthetic_soc_states(bo
// If FCLK is coarse grained, insert individual DPMs.
if (num_fclk_dpms > 2) {
- for (i = 0; i < num_fclk_dpms; i++) {
+ for (j = 0; j < num_fclk_dpms; j++) {
entry.dcfclk_mhz = 0;
- entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
+ entry.fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
@@ -2976,7 +2981,7 @@ static int build_synthetic_soc_states(bo
// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
i = 0;
- while (i < *num_entries - 1) {
+ while (i < ((int)*num_entries - 1)) {
if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1724,7 +1724,8 @@ static void mode_support_configuration(s
void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
{
struct vba_vars_st *v = &mode_lib->vba;
- int i, j, start_state;
+ int i, start_state;
+ unsigned int j;
unsigned int k, m;
unsigned int MaximumMPCCombine;
unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;
@@ -2030,7 +2031,7 @@ void dml32_ModeSupportAndSystemConfigura
mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage
&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible;
- for (i = start_state; i < v->soc.num_states; i++) {
+ for (i = start_state; i < (int)v->soc.num_states; i++) {
for (j = 0; j < 2; j++) {
mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;
mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;
@@ -2307,7 +2308,7 @@ void dml32_ModeSupportAndSystemConfigura
}
}
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.ExceededMultistreamSlots[i] = false;
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
@@ -2410,7 +2411,7 @@ void dml32_ModeSupportAndSystemConfigura
}
}
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
if (mode_lib->vba.BlendingAndTiming[k] == k
@@ -2427,7 +2428,7 @@ void dml32_ModeSupportAndSystemConfigura
}
}
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;
mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
@@ -2445,7 +2446,7 @@ void dml32_ModeSupportAndSystemConfigura
}
}
- for (i = start_state; i < v->soc.num_states; i++) {
+ for (i = start_state; i < (int)v->soc.num_states; i++) {
mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
if (mode_lib->vba.BlendingAndTiming[k] == k) {
@@ -2482,7 +2483,7 @@ void dml32_ModeSupportAndSystemConfigura
/* Check DSC Unit and Slices Support */
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
mode_lib->vba.NotEnoughDSCUnits[i] = false;
mode_lib->vba.NotEnoughDSCSlices[i] = false;
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
@@ -2517,7 +2518,7 @@ void dml32_ModeSupportAndSystemConfigura
}
/*DSC Delay per state*/
- for (i = start_state; i < v->soc.num_states; ++i) {
+ for (i = start_state; i < (int)v->soc.num_states; ++i) {
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(
mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
@@ -2531,7 +2532,7 @@ void dml32_ModeSupportAndSystemConfigura
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
- for (j = 0; j <= mode_lib->vba.NumberOfActiveSurfaces - 1; j++) {
+ for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; j++) {
if (mode_lib->vba.BlendingAndTiming[k] == m &&
mode_lib->vba.RequiresDSC[i][m] == true) {
mode_lib->vba.DSCDelayPerState[i][k] =
@@ -2682,7 +2683,7 @@ void dml32_ModeSupportAndSystemConfigura
mode_lib->vba.SurfaceSizeInMALL,
&mode_lib->vba.ExceededMALLSize);
- for (i = start_state; i < v->soc.num_states; i++) {
+ for (i = start_state; i < (int)v->soc.num_states; i++) {
for (j = 0; j < 2; j++) {
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
mode_lib->vba.swath_width_luma_ub_this_state[k] =
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -6318,7 +6318,7 @@ bool dml32_CalculateDETSwathFillLatencyH
enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[],
enum unbounded_requesting_policy UseUnboundedRequesting)
{
- int k;
+ unsigned int k;
double SwathSizeAllSurfaces = 0;
double SwathSizeAllSurfacesInFetchTimeUs;
double DETSwathLatencyHidingUs;
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -211,8 +211,8 @@ static void dcn321_insert_entry_into_tab
unsigned int *num_entries,
struct _vcs_dpi_voltage_scaling_st *entry)
{
- int i = 0;
- int index = 0;
+ unsigned int i = 0;
+ unsigned int index = 0;
dc_assert_fp_enabled();
@@ -237,7 +237,7 @@ static void dcn321_insert_entry_into_tab
static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
unsigned int index)
{
- int i;
+ unsigned int i;
if (*num_entries == 0)
return;
@@ -265,19 +265,19 @@ static void sort_entries_with_same_bw(st
unsigned int end_index = 0;
unsigned int current_bw = 0;
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i + 1 < *num_entries; i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
current_bw = table[i].net_bw_in_kbytes_sec;
start_index = i;
end_index = ++i;
- while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw))
+ while ((i + 1 < *num_entries) && (table[i+1].net_bw_in_kbytes_sec == current_bw))
end_index = ++i;
}
if (start_index != end_index) {
- for (int j = start_index; j < end_index; j++) {
- for (int k = start_index; k < end_index; k++) {
+ for (unsigned int j = start_index; j < end_index; j++) {
+ for (unsigned int k = start_index; k < end_index; k++) {
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
swap_table_entries(&table[k], &table[k+1]);
}
@@ -296,7 +296,7 @@ static void sort_entries_with_same_bw(st
*/
static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- for (int i = 0; i < (*num_entries - 1); i++) {
+ for (unsigned int i = 0; i + 1 < *num_entries; i++) {
if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
(table[i].fabricclk_mhz > table[i+1].fabricclk_mhz))
@@ -344,7 +344,8 @@ static int override_max_clk_values(struc
static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
- int i, j;
+ int i;
+ unsigned int j, k;
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
@@ -431,8 +432,8 @@ static int build_synthetic_soc_states(bo
entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
// Insert all the DCFCLK STAs
- for (i = 0; i < num_dcfclk_stas; i++) {
- entry.dcfclk_mhz = dcfclk_sta_targets[i];
+ for (k = 0; k < num_dcfclk_stas; k++) {
+ entry.dcfclk_mhz = dcfclk_sta_targets[k];
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
@@ -451,10 +452,10 @@ static int build_synthetic_soc_states(bo
dcn321_insert_entry_into_table_sorted(table, num_entries, &entry);
// Insert the UCLK DPMS
- for (i = 0; i < num_uclk_dpms; i++) {
+ for (k = 0; k < num_uclk_dpms; k++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = 0;
- entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
+ entry.dram_speed_mts = bw_params->clk_table.entries[k].memclk_mhz * 16;
get_optimal_ntuple(&entry);
entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
@@ -463,9 +464,9 @@ static int build_synthetic_soc_states(bo
// If FCLK is coarse grained, insert individual DPMs.
if (num_fclk_dpms > 2) {
- for (i = 0; i < num_fclk_dpms; i++) {
+ for (k = 0; k < num_fclk_dpms; k++) {
entry.dcfclk_mhz = 0;
- entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
+ entry.fabricclk_mhz = bw_params->clk_table.entries[k].fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
@@ -489,7 +490,7 @@ static int build_synthetic_soc_states(bo
// ratios (by derate, are exact).
// Remove states that require higher clocks than are supported
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz ||
table[i].fabricclk_mhz > max_clk_data.fclk_mhz ||
table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16)
@@ -519,7 +520,7 @@ static int build_synthetic_soc_states(bo
// coarse grained DPMs and remove duplicates.
// Round up UCLKs
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_uclk_dpms; j++) {
if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
@@ -530,7 +531,7 @@ static int build_synthetic_soc_states(bo
// If FCLK is coarse grained, round up to next DPMs
if (num_fclk_dpms > 2) {
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_fclk_dpms; j++) {
if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
@@ -541,7 +542,7 @@ static int build_synthetic_soc_states(bo
}
// Otherwise, round up to minimum.
else {
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
if (table[i].fabricclk_mhz < min_fclk_mhz) {
table[i].fabricclk_mhz = min_fclk_mhz;
}
@@ -549,7 +550,7 @@ static int build_synthetic_soc_states(bo
}
// Round DCFCLKs up to minimum
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
table[i].dcfclk_mhz = min_dcfclk_mhz;
}
@@ -557,7 +558,7 @@ static int build_synthetic_soc_states(bo
// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
i = 0;
- while (i < *num_entries - 1) {
+ while (i < (int)*num_entries - 1) {
if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
@@ -567,9 +568,8 @@ static int build_synthetic_soc_states(bo
}
// Fix up the state indicies
- for (i = *num_entries - 1; i >= 0 ; i--) {
+ for (i = (int)*num_entries - 1; i >= 0 ; i--)
table[i].state = i;
- }
return 0;
}
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -233,7 +233,7 @@ void dcn35_update_bw_bounding_box_fpu(st
struct clk_limit_table *clk_table = &bw_params->clk_table;
struct _vcs_dpi_voltage_scaling_st *clock_limits =
dc->scratch.update_bw_bounding_box.clock_limits;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
@@ -440,7 +440,8 @@ int dcn35_populate_dml_pipes_from_contex
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -266,7 +266,7 @@ void dcn351_update_bw_bounding_box_fpu(s
struct clk_limit_table *clk_table = &bw_params->clk_table;
struct _vcs_dpi_voltage_scaling_st *clock_limits =
dc->scratch.update_bw_bounding_box.clock_limits;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+ unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
@@ -472,7 +472,8 @@ int dcn351_populate_dml_pipes_from_conte
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ int pipe_cnt;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -304,7 +304,7 @@ bool get_is_phantom_pipe(struct display_
static void fetch_socbb_params(struct display_mode_lib *mode_lib)
{
soc_bounding_box_st *soc = &mode_lib->vba.soc;
- int i;
+ unsigned int i;
// SOC Bounding Box Parameters
mode_lib->vba.ReturnBusWidth = soc->return_bus_width_bytes;
@@ -946,7 +946,7 @@ static void fetch_pipe_params(struct dis
*/
static void cache_debug_params(struct display_mode_lib *mode_lib)
{
- int k = 0;
+ unsigned int k = 0;
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++)
mode_lib->vba.CachedActiveDRAMClockChangeLatencyMargin[k] = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
next prev parent reply other threads:[~2026-08-20 15:07 UTC|newest]
Thread overview: 232+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-20 14:52 [PATCH 7.1 000/228] 7.1.10-rc1 review Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 001/228] block: stop the timeout timer when releasing a never added disk Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 002/228] selinux: require every boolean value to be defined Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 003/228] selinux: reject a class permission count below its inherited common Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 004/228] selinux: do not cancel a policy conversion that never started Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 005/228] selinux: reject an unclaimed class value in security_get_classes() Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 006/228] selinux: reject a permission value exceeding the class permission count Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 007/228] mptcp: reclaim forward-allocated memory on RX path errors Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 008/228] selftests: mptcp: join: mark tests with data corruption as failed Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 009/228] mptcp: avoid combining some incoming suboptions Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 010/228] mptcp: options: reset DSS fields in case of unexpected size Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 011/228] mptcp: pm: fix data race in add_addr timer callback Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 012/228] mptcp: fastopen: only mark MPTFO subflows with SYN data Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 013/228] s390/qeth: validate user buffer length in SNMP and ARP query ioctls Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 014/228] microblaze: restore the page alignment of swapper_pg_dir Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 015/228] ASoC: codecs: lpass-tx-macro: Fix enum kcontrol accesses Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 016/228] drm/shmem_helper: Check VMA boundaries for PMD mappings Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 017/228] ASoC: SOF: sof-audio: Fix error path in sof_widget_setup_unlocked() Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 018/228] ASoC: SOF: ipc4-pcm: Continue the pipeline trigger in case of IPC timeout Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 019/228] ASoC: cs4265: sort the register default table Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 020/228] ASoC: cs35l45: " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 021/228] ASoC: cs35l41: " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 022/228] ASoC: codecs: lpass-wsa-macro: Fix enum kcontrol accesses Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 023/228] fbdev: bound mode sysfs output to the sysfs buffer Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 024/228] fbdev: clear fb_info->mode before deleting a videomode Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 025/228] fbdev: core: Fix pointer desynchronization in fb_io_read() Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 026/228] drm/panthor: skip zero-sized firmware sections Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 027/228] drm/amdgpu: reject oversized IBs with per-ring packet limits Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 028/228] drm/amdgpu: read TRUNCATE_COORD_MODE on gfx12 Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 029/228] drm/amdgpu/userq: serialize queue map against GPU reset Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 030/228] drm/amd: Disable DP audio spread spectrum for Cyan Skillfish Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 031/228] drm/radeon: restore hardware polling in fence_is_signaled to fix performance regression Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 032/228] drm/amdgpu: Use virtual alloc during coredump Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 033/228] drm/amdgpu: fix JPEG v5.3.0 queue reset failure in DPG mode Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 034/228] drm/amdgpu: fix JPEG v5.0.0 " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 035/228] drm/amdgpu: fix JPEG v4.0.5 " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 036/228] drm/amdgpu: fix aperture iounmap skipped on device removal Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 037/228] drm/amdgpu/gmc12.1: implement tlb inv semaphore Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 038/228] drm/amdgpu/gmc12.1: fix MMHUB0 check in pasid tlb flush Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 039/228] ASoC: SOF: topology: Use acpi mach from the machine driver Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 040/228] Input: xpad - add support for ZENAIM LEVERLESS Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 041/228] Input: cs40l50-vibra - validate custom data from user space Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 042/228] powerpc/pseries: pci - logic bug Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 043/228] Input: synaptics-rmi4 - fix F55 transmitter electrode count typo Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 044/228] Input: focaltech - fix array out-of-bounds in focaltech_process_rel_packet Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 045/228] Input: psxpad-spi - set driver data before use Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 046/228] Input: atkbd - skip deactivate for Xiaomi Book Pro 14s internal keyboard Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 047/228] Input: atkbd - skip deactivate for HONOR ZQC-P Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 048/228] Input: iforce - validate input packet lengths Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 049/228] Input: byd - synchronize timer deletion before freeing private data Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 050/228] powerpc/pseries: lparcfg - fix kbuf[] underflow Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 051/228] powerpc/pseries: papr-phy-attest - validate cmd.length, plug mem leak Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 052/228] Input: synaptics-rmi4 - zero report size on F54 work error Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 053/228] Input: synaptics-rmi4 - bound the F54 report size to the allocated buffer Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 054/228] Input: synaptics-rmi4 - block s_input when F54 queue is busy Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 055/228] Input: synaptics-rmi4 - propagate F54 worker errors to V4L2 queue Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 056/228] Input: hynitron_cstxxx - validate touch count and finger IDs Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 057/228] crypto: starfive - use scatterlist length before DMA mapping Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 058/228] crypto: qce - fix error path in devm_qce_register_algs Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 059/228] gve: fix NULL dereference due to missing ptp adjfine Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 060/228] gpio: sloppy-logic-analyzer: fix use-after-free via debugfs trigger on unbind Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 061/228] selftests/ftrace: Convert ELF entry point to file offset in uprobe test Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 062/228] gve: fix zero-length skb frag with header-split Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 063/228] gpio: ml-ioh: use raw_spinlock_t for the register lock Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 064/228] pmdomain: qcom: rpmhpd: Add missing MXC and MMCX power domains for Eliza Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 065/228] pmdomain: arm: Fix -EINVAL from scmi_pd_set_perf_state() on state 0 Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 066/228] libceph: fix multiple unsafe decodes in decode_locker() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 067/228] pmdomain: mediatek: mfg: initialize prev_o in mtk_mfg_attach_dev() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 068/228] ftrace: Protect direct_functions in ftrace_find_rec_direct Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 069/228] ftrace: Protect direct_functions in update_ftrace_direct_del Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 070/228] ftrace: Protect direct_functions in update_ftrace_direct_mod Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 071/228] ftrace: Fix off-by-one fentry site disable in ftrace_free_mem() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 072/228] openrisc: signal: do not restore privileged SR bits on sigreturn Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 073/228] Input: sur40 - fix input device registration ordering Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 074/228] Input: sur40 - fix V4L error path cleanup Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 075/228] libceph: Avoid using invalid osd indices from primary_temp Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 076/228] ceph: fix MDS random selection readiness predicate Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 077/228] libceph: fix OOB read in decode_watchers() via missing bounds check Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 078/228] libceph: tolerate addrvecs with multiple entries of the same type Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 079/228] mmc: omap_hsmmc: fix busy_timeout overflow in ns conversion on 32-bit Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 080/228] mmc: sdhci: unmap the bounce buffer before device release Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 081/228] pmdomain: mediatek: fix remaining %pOF after of_node_put() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 082/228] mmc: sdhci: make tuning_err a signed int Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 083/228] pmdomains: mediatek: Avoid setting RTFFs CLK_DIS before NRESTORE Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 084/228] mmc: atmel-mci: Fix use-after-free in atmci_remove due to race condition Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 085/228] drm/connector/hdmi: Fix out of bounds memory read Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 086/228] mmc: loongson2: Fix sg iteration in data reorder functions Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 087/228] pmdomain: mediatek: Fix mt8183 hang on boot Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 088/228] riscv: hwprobe: Register unaligned probes before usermode Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 089/228] drm/xe: Order ring writes before ring tail updates Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 090/228] drm/xe: Fix xe_device_probe() failure Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 091/228] drm/xe/guc_ads: allocate UM queues in a separate BO Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 092/228] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 093/228] drm/xe/guc_ads: use uncached mapping for UM queue BO Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 094/228] drm/radeon: fix autosuspend cleanup during teardown Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 095/228] s390/vfio_ccw: Free all memory if cp_init() fails Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 096/228] s390/vfio_ccw: Limit the number of channel program segments Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 097/228] s390/vfio_ccw: Cancel existing workqueues Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 098/228] s390/vfio_ccw: Ensure index for read/write regions are within range Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 099/228] s390/vfio_ccw: Ensure first IDAW remains constant Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 100/228] s390/vfio_ccw: Fix out of bounds check on CCW array Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 101/228] s390/vfio_ccw: Move cp cleanup out of not operational Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 102/228] s390/vfio_ccw: Selectively expand io_mutex Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 103/228] s390/vfio_ccw: Calculate idal length based on idaw type Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 104/228] s390/vfio_ccw: Implement a crw lock Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 105/228] s390/zcrypt: Fix CPRB memory allocation in zcrypt misc code Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 106/228] s390/zcrypt: Improve CCA CPRB length and overflow checks Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 107/228] s390/zcrypt: Improve EP11 " Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 108/228] s390/zcrypt: Improve EP11 CPRB domain handling with ASN.1 parsing Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 109/228] s390/zcrypt: Pad trailing CCA or EP11 message with zeros Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 110/228] drm/amd/display: Fix NULL pointer dereference in amdgpu_dm_crtc_set_vblank() Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 111/228] drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 112/228] drm/amd/display: fix BT.2020 YCbCr output CSC matrices for DCE Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 113/228] drm/amdgpu: Reject UVD message with invalid number of h265 refs Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 114/228] drm/amdgpu: Prefer default discovery offset Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 115/228] drm/amdgpu: fix nbif 6.3.1 l1 low power not functional Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 116/228] drm/amdgpu: fix missing check in vm_flush() Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 117/228] drm/amdgpu: check ASPM on the dGPU host link Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 118/228] drm/amdgpu: validate GEM_CREATE domain combinations Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 119/228] drm/amdgpu: Reject UVD message with dimensions above 4096 Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 120/228] drm/amdgpu: Implement insert_end for VCE 3 Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 121/228] drm/amdgpu: Fix UVD min buffer sizes Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 122/228] drm/amdgpu: Fix UVD dpb min size calculation for H264 Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 123/228] drm/amdgpu: Fix UVD decode image min size calculation Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 124/228] drm/amdgpu: disallow multiple FENCE chunks in one submit Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 125/228] xfs: propagate errors from xfs_rtginode_load Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 126/228] xfs: fix off-by-one in rtrefcount btree root level validation Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 127/228] xfs: bounds-check buffer log items dirty bitmap Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 128/228] xfs: mark nonzero sb_gquotino as corrupt on metadir filesystems Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 129/228] xfs: clear zapped attr fork state when bmap repair finds no attr fork Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 130/228] xfs: check cowextsize in xrep_inode_cowextsize Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 131/228] xfs: fix transaction block reservation in xrep_rtbitmap Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 132/228] xfs: zero i_nlink before repair puts inode on unlinked list Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 133/228] xfs: only check mergeability of bnobt records Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 134/228] xfs: dont double-lock when deleting a self-referential directory Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 135/228] xfs: set the prev pointer when reinserting an inode on the unlinked list Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 136/228] xfs: pass runtime errors from xrep_iunlink_mark_ondisk_rec up to callers Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 137/228] xfs: nlink scrub must take IOLOCK before determining ILOCK state Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 138/228] xfs: load next_agino from the correct xfarray in xrep_iunlink_relink_prev Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 139/228] xfs: fix ilock leak on error in xfs_dq_get_next_id Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 140/228] xfs: dont zap the attr fork on repair when there are queued pptr updates Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 141/228] xfs: dont walk off the end of a null sc->sa.agi_bp in AGI repair Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 142/228] xfs: fix allocated inodes that show up in the unlinked list Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 143/228] xfs: fix another iunlink infinite loop bug in online fsck Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 144/228] xfs: dont return EFSCORRUPTED when scrubbing corrupt parent pointers Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 145/228] xfs: avoid UAF on sc->tempip in xrep_tempfile_create Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 146/228] xfs: fix exchange-range reflink flag clearing issue with INO1_WRITTEN Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 147/228] xfs: dont swallow dquot recovery verification errors Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 148/228] xfs: dont ignore runtime errors in xrep_iunlink_reload_next Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 149/228] xfs: check xfarray iteration errors when committing unlinked inode lists Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 150/228] xfs: check v5 superblock features early Greg Kroah-Hartman
2026-08-20 14:54 ` Greg Kroah-Hartman [this message]
2026-08-20 14:54 ` [PATCH 7.1 152/228] drm/amd/display: Fix warnings Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 153/228] ceph: avoid fs reclaim while using current->journal_info Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 154/228] ceph: fix hanging __ceph_get_caps() with stale mds_wanted Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 155/228] ASoC: tas2562: Validate values for volume writes Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 156/228] drm/mediatek: Convert legacy DRM logging to drm_* helpers in mtk_dsi.c Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 157/228] drm/mediatek: mtk_dsi: Enable HS clock only at pre-enable Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 158/228] drm/amdkfd: Add bounds check for CRAT subtype length Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 159/228] net: rename netdev_ops_assert_locked() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 160/228] net: expect instance lock in netdev_queue_get_dma_dev() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 161/228] ASoC: SOF: ipc4-topology: Refresh copier IPC payload before widget setup Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 162/228] clk: qcom: dispcc-eliza: Fix disp_cc_mdss_mdp_clk_src RCG stall on Eliza EVK Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 163/228] optee: ffa: Add NULL check in optee_ffa_lend_protmem Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 164/228] clk: spacemit: k3: fix USB2 bus clock Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 165/228] clk: spacemit: k3: set hdma clock as critical Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 166/228] arm64: tegra: Add EL2 virtual timer interrupt for Tegra194 Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 167/228] crypto: ccm - Set rfc4309 maxauthsize from child Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 168/228] crypto: tegra - fix rctx->cryptlen calculation in tegra_gcm_do_one_req() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 169/228] rhashtable: fix false-positive lockdep splat on rhltable destruction Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 170/228] gpiolib: Check gc->get_direction() before calling gpiod_get_direction() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 171/228] regulator: fp9931: Fix VPOS/VNEG voltage selector table Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 172/228] af_unix: Unlink scc_entry in unix_del_edge() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 173/228] ovpn: fix NULL dereference when killing missing key Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 174/228] ovpn: finish crypto callback cleanup before peer release Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 175/228] riscv: ftrace: Fix ftrace_modify_call failure on kprobed functions Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 176/228] scsi: core: pair EH runtime PM get and put Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 177/228] perf: Reject exited events as group leaders Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 178/228] sctp: validate cookie AUTH state before use Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 179/228] ALSA: usb-audio: Fix mixer regression on SteelSeries Arctis Nova 5 Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 180/228] riscv: lib: Fix ZBB strnlen reading past count boundary Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 181/228] ovpn: run deferred work on a module-owned workqueue Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 182/228] ovpn: defer key slot crypto freeing to workqueue Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 183/228] rseq: Prevent hard lockup on granted time slice extension Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 184/228] gpio: ml-ioh: share the register lock across channels Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 185/228] ASoC: tas2781: fix clang build error for goto bypassing cleanup variable Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 186/228] tick: Include ktime.h and jiffies.h in linux/tick.h Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 187/228] netfilter: ipset: fix refcount race between list:set GC and swap Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 188/228] ipvs: revalidate ihl to prevent out-of-bounds access Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 189/228] netfilter: nf_tables_offload: suppress WARN_ON_ONCE for ENOMEM in abort path Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 190/228] netfilter: flowtable: publish GC-visible tuple last Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 191/228] netfilter: ipset: fix list type element drift bug Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 192/228] netfilter: ipset: let destroy callbacks adjust ext mem size Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 193/228] eth: bnxt: cancel IRQ notifier before freeing affinity mask Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 194/228] eth: bnxt: keep the aRFS rmap updated when TPH is enabled Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 195/228] eth: bnxt: decrease indent in bnxt_request_irq() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 196/228] eth: bnxt: avoid deadlock when canceling IRQ affinity notifier Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 197/228] ipvlan: inherit needed_headroom and needed_tailroom from phy_dev Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 198/228] macvlan: inherit needed_headroom and needed_tailroom from lowerdev Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 199/228] veth: fix queue index used to wake the peer txq in veth_poll Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 200/228] tcp: fix icsk_ack.ato bitfield overflow Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 201/228] net: phy: realtek: fix EEE advertisement write on the internal PHY MMD path Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 202/228] net: packet: fix wrong transport_header when sending VLAN-tagged frame Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 203/228] net: tap: " Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 204/228] net: ngbe: fix NULL pointer dereference in non-MSI-X interrupt enabling Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 205/228] net/tls: Fail tls_sw_splice_read() after a failed async decrypt Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 206/228] ASoC: xilinx: formatter_pcm: pass aud_drv_data to irq handlers Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 207/228] regmap: sdw-mbq: Fix swap of timeout and retry times Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 208/228] af_packet: Dont send zero-byte data in tpacket_snd() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 209/228] net/sched: act_api: fix TOCTOU NULL deref on a->goto_chain Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 210/228] net/sched: cls_u32: skip hash tables in u32_bind_class() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 211/228] pid: reject allocations through dead ancestor pid namespaces Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 212/228] m68k: Define NR_CPUS to 1 Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 213/228] regmap: sdw-mbq: dont call an unset readable_reg callback Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 214/228] net: ethernet: ti: am65-cpsw-nuss: Fix port_id extraction from SRC TAG Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 215/228] accel/amdxdna: Skip unmapped range in aie2_populate_range() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 216/228] net/sched: cls_bpf: reject dev-bound programs bound to a different device Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 217/228] l2tp: fix tunnel and session refcount leak on seq_file release Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 218/228] firewire: ohci: fix NULL pointer dereference in ar_context_release Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 219/228] drm/xe/pxp: add termination on resume Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 220/228] drm/xe/oa: Fix sync entry leak on OA config emit failure Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 221/228] drm/xe/oa: Check managed mutex initialization errors Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 222/228] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 223/228] drm/xe: Fix a bug in pc_adjust_freq_bounds() Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 224/228] drm/log: Fix division by zero when scale module parameter is 0 Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 225/228] drm/log: Fix out-of-bounds read on empty message length Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 226/228] drm/log: Fix infinite loop when scale is too large for display Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 227/228] spi: virtio: mark device ready before registering the controller Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 228/228] erofs: fix EROFS_FS_ZIP_LZMA_DEFAULT_MAX_STREAMS on some UP platforms Greg Kroah-Hartman
2026-08-20 15:20 ` [PATCH 7.1 000/228] 7.1.10-rc1 review Brett A C Sheffield
2026-08-20 16:00 ` Ronald Warsow
2026-08-20 18:32 ` Pavel Machek
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