From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50EAD45C6FD; Sat, 12 Sep 2026 10:48:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789210086; cv=none; b=bfztWojb2Knir/ZNMH1vH/XUY+gPBgiB2yQLZSaGdx76/gBtGtqQatIkrOxdXaERQjWiZUMbe2L5hQyNO/LKSd8ocw+08C3a+QYaaS4iPhpT9SPX32WmZ+t/ablacFlnW1iz9HQ2p9Ya0TJd2SIDS57Ws6Y7Ldiuv+PXlJDLeDc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789210086; c=relaxed/simple; bh=FhAlyDVlwuHj9TFukxCIaUiDs/122iABqNyYDJG3yKM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GQ4T/tuu7rYjR28SgNURTN8fbVj9ZSPUxTBXnDp/J8mfxmyheGjg6xf04560xP+NwS02YwIMTQAOb3QaMBZudsTngwlrIVlsY4ypQO3PCeuL9MqhKvuRUqOH7vt3P4N1ddCVrojQ8RMQAqTwUch6YycSU3abcSRvE8OCh2z927I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=njVqPktd; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="njVqPktd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16FFD1F000FF; Sat, 12 Sep 2026 10:48:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1789210085; bh=/+18UHypG4xAfgKFzMMdiKMh63zvya55WXvBUQMvFUk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=njVqPktdrVlC7+QwO8AJW3F7AkAwBFTTDootrZZTBBqTcOjD7ekJP0irqCfueocLl czY0cYQthSR4/SOV9M31LIAM0krSZXHrFycSdq71hfqlvFoLBi5Xo77xyFqPVL5TSs RH70j4aG+utbOte7EOfdgAyRzg22yuF0kdZT7yhE= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Simon Glass , Linus Walleij , Sasha Levin Subject: [PATCH 6.18 0953/1518] pinctrl: rockchip: Reset the pin count when recalculating SoC data Date: Sat, 12 Sep 2026 08:52:02 +0200 Message-ID: <20260912065645.016131117@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260912065623.398859879@linuxfoundation.org> References: <20260912065623.398859879@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Simon Glass [ Upstream commit 5b695c191cc85f0fd62eec885b55d01468dc9f2c ] rockchip_pinctrl_get_soc_data() mutates the static per-SoC data. The iomux and drive offsets are recalculated idempotently, since a rerun anchors at the values calculated before, but the total pin count only accumulates: each run adds every bank's pins again. When the probe is deferred and runs a second time, nr_pins doubles and every bank's pin_base shifts, so later pin lookups resolve to the wrong bank and the wrong registers. Reset the pin count at the start of the calculation, so that a rerun produces the same values. This is verified on a Luckfox Pico Mini B (RV1103, with the pending RV1106 series applied) by forcing the probe to defer once: without this patch the second probe calculates nr_pins=304 instead of 152 and no GPIO bank comes up; with it the recalculation matches the first run and all banks work. Fixes: d3e5116119bd ("pinctrl: add pinctrl driver for Rockchip SoCs") Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.org?part=4 Assisted-by: Claude:claude-opus-5 Signed-off-by: Simon Glass Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-rockchip.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index f1cba3d2367a3..834229831de99 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3675,6 +3675,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( pmu_offs = ctrl->pmu_mux_offset; drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; + + /* + * This function mutates the static per-SoC data. Most of it is + * idempotent: recalculated iomux and drv offsets anchor at the + * values calculated by a previous run. The pin count is not, so + * reset it here; otherwise it accumulates when the probe runs + * again after a probe deferral, shifting every bank's pin_base. + */ + ctrl->nr_pins = 0; + bank = ctrl->pin_banks; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0; -- 2.53.0