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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?VQAq+XXXbFBy1VWY4njZQCLbTw5nZht0InFyc1TNRRFGWf5lBGxegmZifKY4?= =?us-ascii?Q?11NGBjkYapIrxBmQDfDQG/ZkWlWDme8CB8Lkn4c9WJUxEM4OLaqZ9InhXDdX?= =?us-ascii?Q?hJz8ARyIkdGR8zx+9VH+/+847exwU8R7CcIqIfiLeJYMTP3u+F1Iu0uk1Ftx?= =?us-ascii?Q?rcaT78k1DFvyM32MhQArTAm+mcfaVbpXve6Ho1gklZ4r0ny6sWEr7oOeOoWq?= =?us-ascii?Q?2iE4TVh13QLU7vj4ZUo1Kxk538YPmGwtyulNUZ7pHHV03hRSC6J/iAnCJ4W5?= =?us-ascii?Q?IOYfhjloGe3JIt3F5Jxx4m6K3olbg9uEojiiQrXKzYMTNRIUXiV9Ns27PF23?= =?us-ascii?Q?M+m/MG6Jz/YD/LkKv0Raya6fyomXXXsfaMYcL4PBV/3N0u67164wLULrk3te?= =?us-ascii?Q?lh7Kc8NuaJnsRu5N4chyQYUA1cPJ3qcabqWh28/NUd+1H0ATEZ7n9eiBtcWf?= =?us-ascii?Q?0T0dyJJzeuzuifH41gU5TXpZuJ6hBBC0hq89SU3gTO+25mFbQkZ7z+ePTC6Z?= =?us-ascii?Q?HhRvxS9BL6r59bTaK9YIbAKgUj/fa9XUi2gZPAWlppI6UKusVF8OLADUxBXL?= =?us-ascii?Q?0yzhDJU87bSxqSw7FnNW9HdxLwFuzGlFRS6OJcMtmofcwX+HmqUlEs0uAgsE?= =?us-ascii?Q?gbGK7A54wwbZiN0Rs/+u2pqhemILY/Ruhcq7KwUcIrYSLi+bRPZ54RoPICze?= =?us-ascii?Q?uAXytAkHKxeilkNt57BXLzYOE7jN8Y7zANXGJRLyNWizkEZl/KtJztxE6LaZ?= =?us-ascii?Q?VGbWU+876mX9dWvUC/3O7kkiVPZYJipiw1NBWzvYaQMKH6/hlY9yOJkwvDO8?= =?us-ascii?Q?l+8J9wtMsiQjUWuLOFHH5C3Sh1PnPNBWWzFbPqeToboux4j9oeJ3Lu3PJUMR?= =?us-ascii?Q?seY+9kld1UmmYJbwwrNBhcS2C9188bXD6zYij+gJOFsYgTMbjJLxtMMjND1X?= =?us-ascii?Q?x71VdA8lWgdK/HBiXx8J+VIgYUxAaB2GDMB9kmU49l56JsUBpOqWZEPkrfXn?= =?us-ascii?Q?a8hHaR8PWkTS9iJ5ThbD1eSudiDCvGnPznMCKhpzd88VBFUl7n6g7sUVnA0t?= =?us-ascii?Q?MRY4vry8owORSKHzjP5XylRW3n1wYWR0f6GRvO3+JPVLt0K356d99DISQu/M?= =?us-ascii?Q?96kKBsv9HdSH871beuLoDuEJPbOUORR2fX0vxffsgb6IBFnSkjwSNDaUecjX?= =?us-ascii?Q?I4T/4qIJHJDLDZ0fe89+GNAz5Q5k2pNQShMIhVAP2bkNUvlQI+7cu5VVyaJZ?= =?us-ascii?Q?hX6KfnnTWCJ/RaN6OJuQsQPwqwVNdXbQsxEoO++rhP/jx1re1F/O29IJAxoK?= =?us-ascii?Q?xAIAae+TDKBJOX4aO1bna+l3jg9DTqj3sy8xLrczSX976kb4JI+7+6L4YtLy?= =?us-ascii?Q?cAVCdNJzyX1BNFTGFQ4zt2/FHGh0UxrDAHvViDmgzsnR588OuMCVWIE7IUi5?= =?us-ascii?Q?6hh5bBzZBHYaZ2FnUu391IwnD3CoceZPHBspSAMrXAp36i1s/XUNIqJzyqxj?= =?us-ascii?Q?NByBvdS5USEvCbaa3MqX/LqAXk7kUsZBPTJzsoFIkIKpsCR6N9b5o5iK+H0Z?= =?us-ascii?Q?WILsj1U31oeiAR+wJ2oEDJvyQ4Z/12N4YJZYs9XanzsE1v6A2DSHKCf12nh0?= =?us-ascii?Q?QomLleb9VCEzEUhWq+MLQrUkZ2N4pCy1Ojc9B3EFCAsYDv8+/jJqf7n5YLLb?= =?us-ascii?Q?fj9iVYYUTnV5KAIvk23UP0rzbJmpxTDOuZIDoJ4lvRIyv1tZ?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1c082f8a-575b-4eb0-9ca1-08df14bdd248 X-MS-Exchange-CrossTenant-AuthSource: CHBPR12MB731189.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2026 13:16:02.2672 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dqF8AheJJIn6/WpjXjSZffgr9ugO5RrEu7qrvhMbT8+U4FHDJkWOEcCVkcABUF2M X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF266051432 On Thu, Sep 17, 2026 at 10:24:08AM +0100, Mark Rutland wrote: > Hi Jason, > > Nit on terminology below. > > On Wed, Sep 16, 2026 at 09:27:42PM -0300, Jason Gunthorpe wrote: > > The erratum (MMU-700: #3777127, S3: #3673557) deals with under > > invalidation of a CONT PTE grouping in the SMMU. The recommended work > > around is to use a Range Invalidate (RIL) that spans the entire CONT. The > > only user of CONT in the kernel right now is through SVA sharing a CPU > > page table that contains a CONT created by the mm. > > As someone familiar with VMSA, I've never seen "RIL" used to describe a > range invalidate and I think using that in the code below is confusing. > I *think* "RIL" has come from "SMMUv3.2-RIL", which is the SMMU feature > for Range Invalidate *and* Level hint, where "RI" is Range Invalidate, > and "L" is Level. Yes, drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h:#define IDR3_RIL (1 << 10) Unfortunately I've noticed a couple of places like this where the SMMU terminology and VMSA differ a little bit. In these cases we've historically choosen the SMMU naming in the SMMU driver to be consistent with its spec.. I've definately seen this gets confusing when talking to people familiar with the CPU spec and IP. I had guessed it ment "Rang InvaLidate", but you are right: RIL, bit [10] Range-based Invalidations and Level hint support for TLBI. The value of this field is an IMPLEMENTATION DEFINED choice of: The driver also calls it ARM_SMMU_FEAT_RANGE_INV, but I thought range_inv everwhere made some very long names. > Can we please spell that out as "range invalidate" or "range op" > (matching the arm64 architecture code) rather than "RIL"? > That'll be easier to follow, especially as nothing in the code mentions > what "RIL" means -- that's only mentioned in this commit message. The whole series uses ril as a shorthand for IDR3_RIL, and the spec often does the same: [25:20] SCALE Range invalidation scale. * See below for use of this field in range invalidation. * When TG == 0b00 this field is RES0. * If SMMU_IDR3.RIL == 0, this field is RES0. ^^^^^^^^^^^ So I'm certainly sympathetic, but I don't know we should diverge the driver from the language in it's own spec. Do you have a recommendation for a suitable short name? It is meaningful work to rename everything in this series.. Will? Thanks, Jason