diff for duplicates of <20260917151554.047755815@linuxfoundation.org> diff --git a/a/1.txt b/N1/1.txt index 3a9911d..35d751a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,38 +1,215 @@ -6.18-stable review patch. If anyone has any objections, please let me know. +6.12-stable review patch. If anyone has any objections, please let me know. ------------------ -From: Parth Pancholi <parth.pancholi@toradex.com> +From: Ciprian Regus <ciprian.regus@analog.com> -[ Upstream commit 6b2bb5438bcfd7bad868665cd2aed1caf9ba3f2b ] +[ Upstream commit 31bc75f17c1f5ff989fa896aae3e4e411d9b0b7a ] -Enable the pre_enable_prev_first flag on the tc358768 bridge to reverse -the pre-enable order, calling bridge pre_enable before panel prepare. -This ensures the bridge is ready before sending panel init commands in -the case of panels sending init commands in panel prepare function. +The OA TC6 standard registers are currently exported in a header file. +Add the OA_TC6_ prefix to the register address and subfield mask macros +to avoid future naming conflicts. -Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> -Tested-by: João Paulo Gonçalves <joao.goncalves@toradex.com> # Toradex Verdin AM62 -Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> -Link: https://patch.msgid.link/20260311-tc358768-v2-2-e75a99131bd5@ideasonboard.com -Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> +Reviewed-by: Andrew Lunn <andrew@lunn.ch> +Signed-off-by: Ciprian Regus <ciprian.regus@analog.com> +Link: https://patch.msgid.link/20260708-adin1140-driver-v5-6-4aca7b51a58b@analog.com +Signed-off-by: Paolo Abeni <pabeni@redhat.com> +Stable-dep-of: 172c974113bf ("net: ethernet: oa_tc6: Improve the error recovery") Signed-off-by: Sasha Levin <sashal@kernel.org> --- - drivers/gpu/drm/bridge/tc358768.c | 2 ++ - 1 file changed, 2 insertions(+) + drivers/net/ethernet/oa_tc6.c | 37 ++++++++++++++++---------------- + include/linux/oa_tc6.h | 40 +++++++++++++++++------------------ + 2 files changed, 39 insertions(+), 38 deletions(-) -diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c -index fbdc44e162293..b7a9d3fca07ea 100644 ---- a/drivers/gpu/drm/bridge/tc358768.c -+++ b/drivers/gpu/drm/bridge/tc358768.c -@@ -448,6 +448,8 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, - DRM_MODE_CONNECTOR_DSI); - if (IS_ERR(bridge)) - return PTR_ERR(bridge); -+ -+ bridge->pre_enable_prev_first = true; +diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c +index 6a01c5e3f14c6..85bd55de36197 100644 +--- a/drivers/net/ethernet/oa_tc6.c ++++ b/drivers/net/ethernet/oa_tc6.c +@@ -396,7 +396,7 @@ static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc6) + if (ret) + return ret; + +- if (!(regval & STDCAP_DIRECT_PHY_REG_ACCESS)) ++ if (!(regval & OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS)) + return -ENODEV; + + return 0; +@@ -589,7 +589,7 @@ static int oa_tc6_read_status0(struct oa_tc6 *tc6) + + static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) + { +- u32 regval = RESET_SWRESET; ++ u32 regval = OA_TC6_RESET_SWRESET; + int ret; + + ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval); +@@ -598,7 +598,7 @@ static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) + + /* Poll for soft reset complete for every 1ms until 1s timeout */ + ret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval, +- regval & STATUS0_RESETC, ++ regval & OA_TC6_STATUS0_RESETC, + STATUS0_RESETC_POLL_DELAY, + STATUS0_RESETC_POLL_TIMEOUT); + if (ret) +@@ -617,10 +617,10 @@ static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) + if (ret) + return ret; + +- regval &= ~(INT_MASK0_TX_PROTOCOL_ERR_MASK | +- INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | +- INT_MASK0_LOSS_OF_FRAME_ERR_MASK | +- INT_MASK0_HEADER_ERR_MASK); ++ regval &= ~(OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK | ++ OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | ++ OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK | ++ OA_TC6_INT_MASK0_HEADER_ERR_MASK); + + return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); + } +@@ -635,7 +635,7 @@ static int oa_tc6_enable_data_transfer(struct oa_tc6 *tc6) + return ret; + + /* Enable configuration synchronization for data transfer */ +- value |= CONFIG0_SYNC; ++ value |= OA_TC6_CONFIG0_SYNC; + + return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, value); + } +@@ -680,7 +680,7 @@ static void oa_tc6_free_pending_skbs(struct oa_tc6 *tc6) + */ + static void oa_tc6_disable_traffic(struct oa_tc6 *tc6) + { +- u32 regval = INT_MASK0_ALL_INTERRUPTS; ++ u32 regval = OA_TC6_INT_MASK0_ALL_INTERRUPTS; + + tc6->disable_traffic = true; + oa_tc6_free_pending_skbs(tc6); +@@ -710,25 +710,25 @@ static int oa_tc6_process_extended_status(struct oa_tc6 *tc6) + return ret; + } + +- if (FIELD_GET(STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { ++ if (FIELD_GET(OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { + tc6->rx_buf_overflow = true; + oa_tc6_cleanup_ongoing_rx_skb(tc6); + net_err_ratelimited("%s: Receive buffer overflow error\n", + tc6->netdev->name); + return -EAGAIN; + } +- if (FIELD_GET(STATUS0_TX_PROTOCOL_ERROR, value)) { ++ if (FIELD_GET(OA_TC6_STATUS0_TX_PROTOCOL_ERROR, value)) { + netdev_err(tc6->netdev, "Transmit protocol error\n"); + return -ENODEV; } + /* TODO: Currently loss of frame and header errors are treated as + * non-recoverable errors. They will be handled in the next version. + */ +- if (FIELD_GET(STATUS0_LOSS_OF_FRAME_ERROR, value)) { ++ if (FIELD_GET(OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR, value)) { + netdev_err(tc6->netdev, "Loss of frame error\n"); + return -ENODEV; + } +- if (FIELD_GET(STATUS0_HEADER_ERROR, value)) { ++ if (FIELD_GET(OA_TC6_STATUS0_HEADER_ERROR, value)) { + netdev_err(tc6->netdev, "Header error\n"); + return -ENODEV; + } +@@ -1175,9 +1175,10 @@ static int oa_tc6_update_buffer_status_from_register(struct oa_tc6 *tc6) + if (ret) + return ret; + +- tc6->tx_credits = FIELD_GET(BUFFER_STATUS_TX_CREDITS_AVAILABLE, value); +- tc6->rx_chunks_available = FIELD_GET(BUFFER_STATUS_RX_CHUNKS_AVAILABLE, +- value); ++ tc6->tx_credits = FIELD_GET(OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE, ++ value); ++ tc6->rx_chunks_available = ++ FIELD_GET(OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE, value); + + return 0; + } +@@ -1221,7 +1222,7 @@ int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6) + return ret; + + /* Set Zero-Align Receive Frame Enable */ +- regval |= CONFIG0_ZARFE_ENABLE; ++ regval |= OA_TC6_CONFIG0_ZARFE_ENABLE; + + return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval); + } +@@ -1269,7 +1270,7 @@ static int oa_tc6_check_ctrl_protection(struct oa_tc6 *tc6) + if (ret) + return ret; + +- tc6->prot_ctrl = FIELD_GET(CONFIG0_PROTE, regval); ++ tc6->prot_ctrl = FIELD_GET(OA_TC6_CONFIG0_PROTE, regval); + + return 0; + } +diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h +index 97c6ed0bf34df..71cffcb041b1c 100644 +--- a/include/linux/oa_tc6.h ++++ b/include/linux/oa_tc6.h +@@ -13,39 +13,39 @@ + /* OPEN Alliance TC6 registers */ + /* Standard Capabilities Register */ + #define OA_TC6_REG_STDCAP 0x0002 +-#define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) ++#define OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) + + /* Reset Control and Status Register */ + #define OA_TC6_REG_RESET 0x0003 +-#define RESET_SWRESET BIT(0) /* Software Reset */ ++#define OA_TC6_RESET_SWRESET BIT(0) /* Software Reset */ + + /* Configuration Register #0 */ + #define OA_TC6_REG_CONFIG0 0x0004 +-#define CONFIG0_SYNC BIT(15) +-#define CONFIG0_ZARFE_ENABLE BIT(12) +-#define CONFIG0_PROTE BIT(5) ++#define OA_TC6_CONFIG0_SYNC BIT(15) ++#define OA_TC6_CONFIG0_ZARFE_ENABLE BIT(12) ++#define OA_TC6_CONFIG0_PROTE BIT(5) + + /* Status Register #0 */ + #define OA_TC6_REG_STATUS0 0x0008 +-#define STATUS0_RESETC BIT(6) /* Reset Complete */ +-#define STATUS0_HEADER_ERROR BIT(5) +-#define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) +-#define STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) +-#define STATUS0_TX_PROTOCOL_ERROR BIT(0) ++#define OA_TC6_STATUS0_RESETC BIT(6) /* Reset Complete */ ++#define OA_TC6_STATUS0_HEADER_ERROR BIT(5) ++#define OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR BIT(4) ++#define OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) ++#define OA_TC6_STATUS0_TX_PROTOCOL_ERROR BIT(0) + + /* Buffer Status Register */ +-#define OA_TC6_REG_BUFFER_STATUS 0x000B +-#define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) +-#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) ++#define OA_TC6_REG_BUFFER_STATUS 0x000B ++#define OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) ++#define OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) + + /* Interrupt Mask Register #0 */ +-#define OA_TC6_REG_INT_MASK0 0x000C +-#define INT_MASK0_HEADER_ERR_MASK BIT(5) +-#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) +-#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) +-#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) +-#define INT_MASK0_ALL_INTERRUPTS (GENMASK(5, 0) | \ +- GENMASK(12, 7)) ++#define OA_TC6_REG_INT_MASK0 0x000C ++#define OA_TC6_INT_MASK0_HEADER_ERR_MASK BIT(5) ++#define OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) ++#define OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) ++#define OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) ++#define OA_TC6_INT_MASK0_ALL_INTERRUPTS (GENMASK(5, 0) | \ ++ GENMASK(12, 7)) - priv->output.dev = dev; + /* PHY Clause 22 registers base address and mask */ + #define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 -- 2.53.0 diff --git a/a/content_digest b/N1/content_digest index 80a9eb8..e2ed73b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,54 +1,230 @@ - "ref\020260917151551.901433442@linuxfoundation.org\0" + "ref\020260917151539.408551884@linuxfoundation.org\0" "From\0Greg Kroah-Hartman <gregkh@linuxfoundation.org>\0" - "Subject\0[PATCH 6.18 0077/1250] drm/bridge: tc358768: Set pre_enable_prev_first for reverse order\0" - "Date\0Thu, 17 Sep 2026 15:57:52 +0100\0" + "Subject\0[PATCH 6.12 0564/1102] net: ethernet: oa_tc6: Add the OA_TC6_ prefix to standard registers\0" + "Date\0Thu, 17 Sep 2026 16:08:27 +0100\0" "To\0stable@vger.kernel.org\0" "Cc\0Greg Kroah-Hartman <gregkh@linuxfoundation.org>" patches@lists.linux.dev - Parth Pancholi <parth.pancholi@toradex.com> - Francesco Dolcini <francesco.dolcini@toradex.com> - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> - Sasha Levin <sashal@kernel.org> - " Jo\303\243o Paulo Gon\303\247alves <joao.goncalves@toradex.com>\0" + Andrew Lunn <andrew@lunn.ch> + Ciprian Regus <ciprian.regus@analog.com> + Paolo Abeni <pabeni@redhat.com> + " Sasha Levin <sashal@kernel.org>\0" "\00:1\0" "b\0" - "6.18-stable review patch. If anyone has any objections, please let me know.\n" + "6.12-stable review patch. If anyone has any objections, please let me know.\n" "\n" "------------------\n" "\n" - "From: Parth Pancholi <parth.pancholi@toradex.com>\n" + "From: Ciprian Regus <ciprian.regus@analog.com>\n" "\n" - "[ Upstream commit 6b2bb5438bcfd7bad868665cd2aed1caf9ba3f2b ]\n" + "[ Upstream commit 31bc75f17c1f5ff989fa896aae3e4e411d9b0b7a ]\n" "\n" - "Enable the pre_enable_prev_first flag on the tc358768 bridge to reverse\n" - "the pre-enable order, calling bridge pre_enable before panel prepare.\n" - "This ensures the bridge is ready before sending panel init commands in\n" - "the case of panels sending init commands in panel prepare function.\n" + "The OA TC6 standard registers are currently exported in a header file.\n" + "Add the OA_TC6_ prefix to the register address and subfield mask macros\n" + "to avoid future naming conflicts.\n" "\n" - "Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>\n" - "Tested-by: Jo\303\243o Paulo Gon\303\247alves <joao.goncalves@toradex.com> # Toradex Verdin AM62\n" - "Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>\n" - "Link: https://patch.msgid.link/20260311-tc358768-v2-2-e75a99131bd5@ideasonboard.com\n" - "Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>\n" + "Reviewed-by: Andrew Lunn <andrew@lunn.ch>\n" + "Signed-off-by: Ciprian Regus <ciprian.regus@analog.com>\n" + "Link: https://patch.msgid.link/20260708-adin1140-driver-v5-6-4aca7b51a58b@analog.com\n" + "Signed-off-by: Paolo Abeni <pabeni@redhat.com>\n" + "Stable-dep-of: 172c974113bf (\"net: ethernet: oa_tc6: Improve the error recovery\")\n" "Signed-off-by: Sasha Levin <sashal@kernel.org>\n" "---\n" - " drivers/gpu/drm/bridge/tc358768.c | 2 ++\n" - " 1 file changed, 2 insertions(+)\n" + " drivers/net/ethernet/oa_tc6.c | 37 ++++++++++++++++----------------\n" + " include/linux/oa_tc6.h | 40 +++++++++++++++++------------------\n" + " 2 files changed, 39 insertions(+), 38 deletions(-)\n" "\n" - "diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c\n" - "index fbdc44e162293..b7a9d3fca07ea 100644\n" - "--- a/drivers/gpu/drm/bridge/tc358768.c\n" - "+++ b/drivers/gpu/drm/bridge/tc358768.c\n" - "@@ -448,6 +448,8 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,\n" - " \t\t\t\t\t\t DRM_MODE_CONNECTOR_DSI);\n" - " \t\tif (IS_ERR(bridge))\n" - " \t\t\treturn PTR_ERR(bridge);\n" - "+\n" - "+\t\tbridge->pre_enable_prev_first = true;\n" + "diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c\n" + "index 6a01c5e3f14c6..85bd55de36197 100644\n" + "--- a/drivers/net/ethernet/oa_tc6.c\n" + "+++ b/drivers/net/ethernet/oa_tc6.c\n" + "@@ -396,7 +396,7 @@ static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc6)\n" + " \tif (ret)\n" + " \t\treturn ret;\n" + " \n" + "-\tif (!(regval & STDCAP_DIRECT_PHY_REG_ACCESS))\n" + "+\tif (!(regval & OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS))\n" + " \t\treturn -ENODEV;\n" + " \n" + " \treturn 0;\n" + "@@ -589,7 +589,7 @@ static int oa_tc6_read_status0(struct oa_tc6 *tc6)\n" + " \n" + " static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6)\n" + " {\n" + "-\tu32 regval = RESET_SWRESET;\n" + "+\tu32 regval = OA_TC6_RESET_SWRESET;\n" + " \tint ret;\n" + " \n" + " \tret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval);\n" + "@@ -598,7 +598,7 @@ static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6)\n" + " \n" + " \t/* Poll for soft reset complete for every 1ms until 1s timeout */\n" + " \tret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval,\n" + "-\t\t\t\t regval & STATUS0_RESETC,\n" + "+\t\t\t\t regval & OA_TC6_STATUS0_RESETC,\n" + " \t\t\t\t STATUS0_RESETC_POLL_DELAY,\n" + " \t\t\t\t STATUS0_RESETC_POLL_TIMEOUT);\n" + " \tif (ret)\n" + "@@ -617,10 +617,10 @@ static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6)\n" + " \tif (ret)\n" + " \t\treturn ret;\n" + " \n" + "-\tregval &= ~(INT_MASK0_TX_PROTOCOL_ERR_MASK |\n" + "-\t\t INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK |\n" + "-\t\t INT_MASK0_LOSS_OF_FRAME_ERR_MASK |\n" + "-\t\t INT_MASK0_HEADER_ERR_MASK);\n" + "+\tregval &= ~(OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK |\n" + "+\t\t OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK |\n" + "+\t\t OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK |\n" + "+\t\t OA_TC6_INT_MASK0_HEADER_ERR_MASK);\n" + " \n" + " \treturn oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval);\n" + " }\n" + "@@ -635,7 +635,7 @@ static int oa_tc6_enable_data_transfer(struct oa_tc6 *tc6)\n" + " \t\treturn ret;\n" + " \n" + " \t/* Enable configuration synchronization for data transfer */\n" + "-\tvalue |= CONFIG0_SYNC;\n" + "+\tvalue |= OA_TC6_CONFIG0_SYNC;\n" + " \n" + " \treturn oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, value);\n" + " }\n" + "@@ -680,7 +680,7 @@ static void oa_tc6_free_pending_skbs(struct oa_tc6 *tc6)\n" + " */\n" + " static void oa_tc6_disable_traffic(struct oa_tc6 *tc6)\n" + " {\n" + "-\tu32 regval = INT_MASK0_ALL_INTERRUPTS;\n" + "+\tu32 regval = OA_TC6_INT_MASK0_ALL_INTERRUPTS;\n" + " \n" + " \ttc6->disable_traffic = true;\n" + " \toa_tc6_free_pending_skbs(tc6);\n" + "@@ -710,25 +710,25 @@ static int oa_tc6_process_extended_status(struct oa_tc6 *tc6)\n" + " \t\treturn ret;\n" + " \t}\n" + " \n" + "-\tif (FIELD_GET(STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) {\n" + "+\tif (FIELD_GET(OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) {\n" + " \t\ttc6->rx_buf_overflow = true;\n" + " \t\toa_tc6_cleanup_ongoing_rx_skb(tc6);\n" + " \t\tnet_err_ratelimited(\"%s: Receive buffer overflow error\\n\",\n" + " \t\t\t\t tc6->netdev->name);\n" + " \t\treturn -EAGAIN;\n" + " \t}\n" + "-\tif (FIELD_GET(STATUS0_TX_PROTOCOL_ERROR, value)) {\n" + "+\tif (FIELD_GET(OA_TC6_STATUS0_TX_PROTOCOL_ERROR, value)) {\n" + " \t\tnetdev_err(tc6->netdev, \"Transmit protocol error\\n\");\n" + " \t\treturn -ENODEV;\n" " \t}\n" + " \t/* TODO: Currently loss of frame and header errors are treated as\n" + " \t * non-recoverable errors. They will be handled in the next version.\n" + " \t */\n" + "-\tif (FIELD_GET(STATUS0_LOSS_OF_FRAME_ERROR, value)) {\n" + "+\tif (FIELD_GET(OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR, value)) {\n" + " \t\tnetdev_err(tc6->netdev, \"Loss of frame error\\n\");\n" + " \t\treturn -ENODEV;\n" + " \t}\n" + "-\tif (FIELD_GET(STATUS0_HEADER_ERROR, value)) {\n" + "+\tif (FIELD_GET(OA_TC6_STATUS0_HEADER_ERROR, value)) {\n" + " \t\tnetdev_err(tc6->netdev, \"Header error\\n\");\n" + " \t\treturn -ENODEV;\n" + " \t}\n" + "@@ -1175,9 +1175,10 @@ static int oa_tc6_update_buffer_status_from_register(struct oa_tc6 *tc6)\n" + " \tif (ret)\n" + " \t\treturn ret;\n" + " \n" + "-\ttc6->tx_credits = FIELD_GET(BUFFER_STATUS_TX_CREDITS_AVAILABLE, value);\n" + "-\ttc6->rx_chunks_available = FIELD_GET(BUFFER_STATUS_RX_CHUNKS_AVAILABLE,\n" + "-\t\t\t\t\t value);\n" + "+\ttc6->tx_credits = FIELD_GET(OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE,\n" + "+\t\t\t\t value);\n" + "+\ttc6->rx_chunks_available =\n" + "+\t\tFIELD_GET(OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE, value);\n" + " \n" + " \treturn 0;\n" + " }\n" + "@@ -1221,7 +1222,7 @@ int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6)\n" + " \t\treturn ret;\n" + " \n" + " \t/* Set Zero-Align Receive Frame Enable */\n" + "-\tregval |= CONFIG0_ZARFE_ENABLE;\n" + "+\tregval |= OA_TC6_CONFIG0_ZARFE_ENABLE;\n" + " \n" + " \treturn oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval);\n" + " }\n" + "@@ -1269,7 +1270,7 @@ static int oa_tc6_check_ctrl_protection(struct oa_tc6 *tc6)\n" + " \tif (ret)\n" + " \t\treturn ret;\n" + " \n" + "-\ttc6->prot_ctrl = FIELD_GET(CONFIG0_PROTE, regval);\n" + "+\ttc6->prot_ctrl = FIELD_GET(OA_TC6_CONFIG0_PROTE, regval);\n" + " \n" + " \treturn 0;\n" + " }\n" + "diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h\n" + "index 97c6ed0bf34df..71cffcb041b1c 100644\n" + "--- a/include/linux/oa_tc6.h\n" + "+++ b/include/linux/oa_tc6.h\n" + "@@ -13,39 +13,39 @@\n" + " /* OPEN Alliance TC6 registers */\n" + " /* Standard Capabilities Register */\n" + " #define OA_TC6_REG_STDCAP\t\t\t0x0002\n" + "-#define STDCAP_DIRECT_PHY_REG_ACCESS\t\tBIT(8)\n" + "+#define OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS\tBIT(8)\n" + " \n" + " /* Reset Control and Status Register */\n" + " #define OA_TC6_REG_RESET\t\t\t0x0003\n" + "-#define RESET_SWRESET\t\t\t\tBIT(0)\t/* Software Reset */\n" + "+#define OA_TC6_RESET_SWRESET\t\t\tBIT(0)\t/* Software Reset */\n" + " \n" + " /* Configuration Register #0 */\n" + " #define OA_TC6_REG_CONFIG0\t\t\t0x0004\n" + "-#define CONFIG0_SYNC\t\t\t\tBIT(15)\n" + "-#define CONFIG0_ZARFE_ENABLE\t\t\tBIT(12)\n" + "-#define CONFIG0_PROTE\t\t\t\tBIT(5)\n" + "+#define OA_TC6_CONFIG0_SYNC\t\t\tBIT(15)\n" + "+#define OA_TC6_CONFIG0_ZARFE_ENABLE\t\tBIT(12)\n" + "+#define OA_TC6_CONFIG0_PROTE\t\t\tBIT(5)\n" + " \n" + " /* Status Register #0 */\n" + " #define OA_TC6_REG_STATUS0\t\t\t0x0008\n" + "-#define STATUS0_RESETC\t\t\t\tBIT(6)\t/* Reset Complete */\n" + "-#define STATUS0_HEADER_ERROR\t\t\tBIT(5)\n" + "-#define STATUS0_LOSS_OF_FRAME_ERROR\t\tBIT(4)\n" + "-#define STATUS0_RX_BUFFER_OVERFLOW_ERROR\tBIT(3)\n" + "-#define STATUS0_TX_PROTOCOL_ERROR\t\tBIT(0)\n" + "+#define OA_TC6_STATUS0_RESETC\t\t\tBIT(6)\t/* Reset Complete */\n" + "+#define OA_TC6_STATUS0_HEADER_ERROR\t\tBIT(5)\n" + "+#define OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR\tBIT(4)\n" + "+#define OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR\tBIT(3)\n" + "+#define OA_TC6_STATUS0_TX_PROTOCOL_ERROR\tBIT(0)\n" + " \n" + " /* Buffer Status Register */\n" + "-#define OA_TC6_REG_BUFFER_STATUS\t\t0x000B\n" + "-#define BUFFER_STATUS_TX_CREDITS_AVAILABLE\tGENMASK(15, 8)\n" + "-#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE\tGENMASK(7, 0)\n" + "+#define OA_TC6_REG_BUFFER_STATUS\t\t\t0x000B\n" + "+#define OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE\tGENMASK(15, 8)\n" + "+#define OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE\tGENMASK(7, 0)\n" + " \n" + " /* Interrupt Mask Register #0 */\n" + "-#define OA_TC6_REG_INT_MASK0\t\t\t0x000C\n" + "-#define INT_MASK0_HEADER_ERR_MASK\t\tBIT(5)\n" + "-#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK\tBIT(4)\n" + "-#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK\tBIT(3)\n" + "-#define INT_MASK0_TX_PROTOCOL_ERR_MASK\t\tBIT(0)\n" + "-#define INT_MASK0_ALL_INTERRUPTS (GENMASK(5, 0) | \\\n" + "-\t\t\t\t\t\t GENMASK(12, 7))\n" + "+#define OA_TC6_REG_INT_MASK0\t\t\t\t0x000C\n" + "+#define OA_TC6_INT_MASK0_HEADER_ERR_MASK\t\tBIT(5)\n" + "+#define OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK\t\tBIT(4)\n" + "+#define OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK\tBIT(3)\n" + "+#define OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK\t\tBIT(0)\n" + "+#define OA_TC6_INT_MASK0_ALL_INTERRUPTS (GENMASK(5, 0) | \\\n" + "+\t\t\t\t\t\t\t GENMASK(12, 7))\n" " \n" - " \tpriv->output.dev = dev;\n" + " /* PHY Clause 22 registers base address and mask */\n" + " #define OA_TC6_PHY_STD_REG_ADDR_BASE\t\t0xFF00\n" "-- \n" 2.53.0 -165fe323081901777637cdfdb31fbd2fcee6950f3596fa8678b30e0906d485d5 +54a5c6c7e236cb677f814eccdabc04c399087c234cea07d78318ce320350708c
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