From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1B8A4F4D08; Thu, 17 Sep 2026 16:07:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789661277; cv=none; b=oiYgEL04IUDR2Wz7xp3MsQWeelMDhz5jdqIse3CZQZ0BfsxnRcudx1e0ciSEz4Dy2IV2UWP443bpvYpy6IDXeEoUfQC6VbiyuwI/SK2zVovAHEGhfxmasOqox/58WqDZSgye2nCgZTs000TBb8d1BKVWphVBULTH9hdq2gbP5lw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789661277; c=relaxed/simple; bh=kIz1uMU/H8HF+10ITezTlIYROqPIaPqf1oZ5MIuHzUE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AhwVsPb//uvUFkiuOve4GDj6AENcuJzK9TEyyCcHkCzVY+ar4cZGgMp+Mgu/AuBizLZ0alQfq+t4d2SKvTgOuRXU6WMrtJ68+zYHc/ISe+xY8s+KwNs/KiBnymGeYuq2JxdA73WUN+3mP2LZkaGPME2WjbwN5l2HGO6+3OK5+54= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=dpI5BWJU; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="dpI5BWJU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 02B9F1F000FF; Thu, 17 Sep 2026 16:07:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1789661276; bh=v/f8uLX8zumlpgXuyE9gIOXyMmHy1IHPunmrReE/1D8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dpI5BWJUjGFULA9Blq+ekh9qS67RviX8PxrvXoKPVd0qRql0gfxNEa3fEDlWL+ZLM 6Dy5GYE3SP89ajH6gCQ8Dv4+zd+Mr6mjNwINndTfIEs7G+MGj+lXaLQN5Cg1slU4vZ azxl9cj4kelKw8ML6ZvY/UR6o+wsS4cTXVq0XY9U= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Anna Maniscalco , Rob Clark , Robin Murphy , Will Deacon , Sasha Levin Subject: [PATCH 6.18 0142/1250] iommu: arm-smmu-qcom: Ensure smmu is powered up in set_ttbr0_cfg Date: Thu, 17 Sep 2026 15:58:57 +0100 Message-ID: <20260917151555.904198439@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260917151551.901433442@linuxfoundation.org> References: <20260917151551.901433442@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Anna Maniscalco [ Upstream commit 8a0aab012b52b5c044ca3bec523e91f95dd40765 ] arm_smmu_write_context_bank() assumes it is being called with RPM active, but it turns out that is not guaranteed in the path from qcom_adreno_smmu_set_ttbr0_cfg(), so it's possible for the register writes to get lost when configuring the context bank while the GPU is idle, leading to page faults later. Add the RPM calls here to make sure the SMMU is active before we touch it. Signed-off-by: Anna Maniscalco Reviewed-by: Rob Clark Reviewed-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 3b9fb1c71e5f9..f7cb7de80cfb9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -231,6 +231,7 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); struct arm_smmu_cfg *cfg = &smmu_domain->cfg; struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; + int ret; /* The domain must have split pagetables already enabled */ if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) @@ -260,8 +261,16 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); } + ret = pm_runtime_resume_and_get(smmu_domain->smmu->dev); + if (ret < 0) { + dev_err(smmu_domain->smmu->dev, "failed to get runtime PM: %d\n", ret); + return -ENODEV; + } + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); + pm_runtime_put_autosuspend(smmu_domain->smmu->dev); + return 0; } -- 2.53.0