From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FD874EDCBF; Thu, 17 Sep 2026 16:56:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789664194; cv=none; b=GPx8ePSPT3iHz5a9Z1ud6dP1r1DxBnQw7Y03VCluOGiep9qaHyjVWwLCrd1RbojTGwp0d2SjXQEtEugQigDYlj4Z2liReD4zfdXd5DB0Lnl6Y/WJvZpif76PUrWtuwnJfLVlgFbC92YB6PoEyzoTxkfAdarhN4lFZe82urx4RKc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789664194; c=relaxed/simple; bh=V7mCg6BcI5h/xFVhyvphAy5er6TqMyYeR64QzLujW3o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tSTeuYFPJp22MAU63Dk9K5qVDKbsW9nCdmoV8AZuhXGHVwe3coMdeZiDM2HncC9DCPHA1u8t7kvJg/0iB0KCDUsqnNX4THHvcFS1EPxv+bJGtS2bHS9VOsuFBkPATFNSlovluRgENzGMA+SiCcs2yTGM3UDTcsW7l6Jls2TO2JM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=fqXyB4QN; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="fqXyB4QN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E1C81F000FF; Thu, 17 Sep 2026 16:56:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1789664193; bh=dkB0qnGKcQOfjV2guzV612Ora5Tbl7n8MjjFHA+k54U=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=fqXyB4QNE2e9omyYI/0cEaLwmdEkPD5crC1WL4bJDNlwXtwRXR+ai4x+Fp65AarJ7 5/1xbXGjKnTMSDdQ/vKzK1DGb3+Mcq0mz+vE91rJM+9jFAJYuD1MN+GoT63fM+1WUZ a1eksVJ80jUxy2PPnI0o7hjDSr1sOKIvNIZ4NE7w= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Simon Xue , =?UTF-8?q?Sven=20P=C3=BCschel?= , Heiko Stuebner , Joerg Roedel , Sasha Levin Subject: [PATCH 6.18 0289/1250] iommu/rockchip: disable fetch dte time limit Date: Thu, 17 Sep 2026 16:01:24 +0100 Message-ID: <20260917151559.961191074@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260917151551.901433442@linuxfoundation.org> References: <20260917151551.901433442@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Simon Xue [ Upstream commit 8d4346ecd4950ae08cc76a6de327c264e846758c ] Disable the Bit 31 of the AUTO_GATING iommu register, as it causes hangups with the RGA3 (Raster Graphics Acceleration 3) peripheral. The RGA3 register description of the TRM already states that the bit must be set to 1. The vendor kernel sets the bit unconditionally to 1 to fix VOP (Video Output Processor) screen black issues. This patch squashes the 2 vendor kernel commits with the following commit messages: Master fetch data and cpu update page table may work in parallel, may have the following procedure: master cpu fetch dte update page tabl | | (make dte invalid) <- zap iotlb entry | | fetch dte again (make dte invalid) <- zap iotlb entry | | fetch dte again (make dte invalid) <- zap iotlb entry | | fetch dte again (make iommu block) <- zap iotlb entry New iommu version has the above bug, if fetch dte consecutively four times, then it will be blocked. Fortunately, we can set bit 31 of register MMU_AUTO_GATING to 1 to make it work as old version which does not have this issue. This issue only appears on RV1126 so far, so make a workaround dedicated to "rockchip,rv1126" machine type. iommu/rockchip: fix vop blocked and screen black on RK356X and RK3588 RK3568 and RK3588 has the same issue as RV1126/RV1109 that caused by dte fetch time limit, So we can set BIT(31) of register 0x24 default to 1 as a workaround. Signed-off-by: Simon Xue Signed-off-by: Sven Püschel Acked-by: Heiko Stuebner Signed-off-by: Joerg Roedel Signed-off-by: Sasha Levin --- drivers/iommu/rockchip-iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index 0861dd469bd86..2d0dabb0d101a 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -76,6 +76,8 @@ #define SPAGE_ORDER 12 #define SPAGE_SIZE (1 << SPAGE_ORDER) +#define DISABLE_FETCH_DTE_TIME_LIMIT BIT(31) + /* * Support mapping any size that fits in one page table: * 4 KiB to 4 MiB @@ -930,6 +932,7 @@ static int rk_iommu_enable(struct rk_iommu *iommu) struct iommu_domain *domain = iommu->domain; struct rk_iommu_domain *rk_domain = to_rk_domain(domain); int ret, i; + u32 auto_gate; ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); if (ret) @@ -948,6 +951,11 @@ static int rk_iommu_enable(struct rk_iommu *iommu) rk_ops->mk_dtentries(rk_domain->dt_dma)); rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); + + /* Workaround for iommu blocked, BIT(31) default to 1 */ + auto_gate = rk_iommu_read(iommu->bases[i], RK_MMU_AUTO_GATING); + auto_gate |= DISABLE_FETCH_DTE_TIME_LIMIT; + rk_iommu_write(iommu->bases[i], RK_MMU_AUTO_GATING, auto_gate); } ret = rk_iommu_enable_paging(iommu); -- 2.53.0