From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56CCE53160C; Wed, 23 Sep 2026 14:52:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790175148; cv=none; b=N1BdWl+KVFWWZ0+2gEXQnplh1FH+Ij5XNLFx9tGo/NrmGFeaTkgM7iNJL54OBn78fa4CRoo6UgHkYnwiPnPFF7km/c0A4B60wdf9sZXtHlZnBGHglzNDUFqgYkryU63U2jeuNk6Lo3BvQLoGL8wYw8ZbEuMjViUTEhO21wNjmLc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790175148; c=relaxed/simple; bh=EkRMUDNJDEaLEUB51VtlJg1cfVL6iM06SSn0R+wId0A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kSzALFQTg7+SCroQpjj1HItpJcliP8W/ng2DFRvLJGVWDdx8nhtlgA7GJ8kvx+kfjT8MRP9i4frXDvH5BJl4N77rsTaWWsTDqBXDHKMQ+7VgXrEUqLqvvbp0sFtN383+2NxGorupp0R/NI5wWJQGEzeZTL30Yq0DRaRwLra29LA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Qb04wspG; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Qb04wspG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1F601F000FF; Wed, 23 Sep 2026 14:52:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1790175144; bh=KlFKmZT1LriL9JMd8/OYbQ3vjoROg5jzsHgvCscYStw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Qb04wspGVsiPlJjGCbZBRM9zfluz+J8ezmcbsKfSAKf4+hhWTmCZoHU7rK6I/DG3V kSrr5Ae1BxcSqPyEEq3BDUqaGetdnXVHB7u8aic/NdzaRFxrh+ma2UBvERxpC4pjNW FznQsMbJoJEq0FdvbVd5tRWKhCpLzInTmzIXSrWk= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Tzung-Bi Shih , Guenter Roeck Subject: [PATCH 6.18 317/398] watchdog: msc313e: Fix premature reset during timeout update Date: Wed, 23 Sep 2026 16:06:31 +0200 Message-ID: <20260923140651.638910199@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260923140643.441954610@linuxfoundation.org> References: <20260923140643.441954610@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Tzung-Bi Shih commit 22737cfced627ffcb4b5c36d63bb3d4476f63213 upstream. Updating the 32-bit hardware timeout requires writing to two 16-bit registers sequentially. If the watchdog is actively running, this non-atomic update might trigger a premature system reset. Clear the watchdog counter before updating the registers to prevent the timer from timing out prematurely against an intermediate threshold. Fixes: e9800b799464 ("watchdog: Add Mstar MSC313e WDT driver") Cc: stable@vger.kernel.org Signed-off-by: Tzung-Bi Shih Link: https://patch.msgid.link/20260913065126.8350-1-tzungbi@kernel.org Signed-off-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- drivers/watchdog/msc313e_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) --- a/drivers/watchdog/msc313e_wdt.c +++ b/drivers/watchdog/msc313e_wdt.c @@ -47,6 +47,9 @@ static void msc313e_wdt_set_hw_timeout(s { u32 t = timeout * clk_get_rate(priv->clk); + /* Clear before to prevent premature reset during non-atomic updates. */ + writew(1, priv->base + REG_WDT_CLR); + writew(t & 0xffff, priv->base + REG_WDT_MAX_PRD_L); writew((t >> 16) & 0xffff, priv->base + REG_WDT_MAX_PRD_H); writew(1, priv->base + REG_WDT_CLR); @@ -77,6 +80,9 @@ static int msc313e_wdt_stop(struct watch { struct msc313e_wdt_priv *priv = watchdog_get_drvdata(wdev); + /* Clear before to prevent premature reset during non-atomic updates. */ + writew(1, priv->base + REG_WDT_CLR); + writew(0, priv->base + REG_WDT_MAX_PRD_L); writew(0, priv->base + REG_WDT_MAX_PRD_H); writew(0, priv->base + REG_WDT_CLR);