From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF61B51E451; Wed, 30 Sep 2026 18:42:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790793777; cv=none; b=EwSWd5d7qYqVlT+Gi2P2a5I95xJEn1F6WgR1gCCwmxI8xMXauhpSHQlR734vQpLEAo61FdUcn58TXliK2PpPczwgmZCV2WX6s1BsGw5jD04ALVpfJwN7fLZ76pwyySthANGsolXxqlrvuyntKrKft+JJwDDAv7kqnrzLRRUPiM8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790793777; c=relaxed/simple; bh=MrGH/NgxWYLv0uUPYcqQ9gAKgEAzglvZdv74EyVQv4M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PSRq5kAdxfi/ka268CpqaiVLT/dwMFVu42cklJ6C8Et8910MMnhRRv2QYLEALPny1+h7AeFGSvMdWQKXGoSChUdaYg2JRd0kaixjWjbzVNhnXH7Gb3OlNSwVmBQ3CKndVSKhNU0E+rIJ6RFUAYdPhb3ZP89KYGV8ZXeoz07u85w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=yNwiVi3T; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="yNwiVi3T" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56C691F000FF; Wed, 30 Sep 2026 18:42:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1790793775; bh=IzlrO/btLG8VMZQjG5WxI030dBzA6Rf7rkfpU1D1sJA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=yNwiVi3TD5+N2RW67lt89iRU5RZPjA0xGyWtxaUUnakg9ZtcODA/uqq/0UPjAmPcP rqZ3G+3fvNkRlKgqqg09qVuM7B90Z0z4kMH6PEIbaWxvi3Kz0nxMeqsDKKCdVYEWky tfLwaBAhnUGR9EcJ0gJzaMJEXPwqFW63Lwn4IP4c= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dapeng Mi , "Peter Zijlstra (Intel)" , Sasha Levin Subject: [PATCH 6.18 375/395] perf/x86/intel: Update event constraints and cache_extra_regsfor LNL Date: Wed, 30 Sep 2026 17:30:37 +0200 Message-ID: <20260930152348.832757681@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930152340.591469096@linuxfoundation.org> References: <20260930152340.591469096@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Dapeng Mi [ Upstream commit 331c3e4fa39a87560c09bdd878652090ae040b69 ] Update perf hard-coded event constraints and cache_extra_regs[] for Lunarlake according to the latest LNL perfmon events (V1.22). LNL introduces new extra register values for the OCR L3 cache events, so introduce lnc_hw_cache_extra_regs[] and skt_hw_cache_extra_regs[] to reflect the changes. LNL perfmon events: https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_lioncove_core.json https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_skymont_core.json Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-7-dapeng1.mi@linux.intel.com [Backport to 6.18: retain the Lion Cove PEBS constraint additions needed by 7c944595cc43 ("perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints"). Keep the matching regular counter masks for TOPDOWN.MEMORY_BOUND_SLOTS (0x10a4, 0x8) and MEM_INST_RETIRED.ANY (0x87d0, 0x3ff), since that fix removes their PEBS-specific entries and falls back to the regular constraint table. Omit the unrelated cache extra-register tables and PMU initialization changes, which depend on cache-event refactoring and intel_pmu_init_cmt() absent from 6.18. Also omit the unrelated fixed-counter, non-PEBS OCR, 0x00e0, and Skymont constraint updates. No functions are added.] Stable-dep-of: 7c944595cc43 ("perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints") Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/intel/core.c | 3 ++- arch/x86/events/intel/ds.c | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -412,11 +412,12 @@ static struct event_constraint intel_lnc INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), - INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1), + INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8), INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc), INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), + INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff), INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf), --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1218,6 +1218,13 @@ struct event_constraint intel_lnc_pebs_e INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), + INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1), /* OCR.* events */ + INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1), /* OCR.* events */ + + INTEL_FLAGS_UEVENT_CONSTRAINT(0x04a4, 0x1), /* TOPDOWN.BAD_SPEC_SLOTS */ + INTEL_FLAGS_UEVENT_CONSTRAINT(0x08a4, 0x1), /* TOPDOWN.BR_MISPREDICT_SLOTS */ + INTEL_FLAGS_UEVENT_CONSTRAINT(0x10a4, 0x8), /* TOPDOWN.MEMORY_BOUND_SLOTS */ + INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc), INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3), INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ @@ -1227,6 +1234,7 @@ struct event_constraint intel_lnc_pebs_e INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ + INTEL_FLAGS_UEVENT_CONSTRAINT(0x87d0, 0x3ff), /* MEM_INST_RETIRED.ANY */ INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),