From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1136B3264C2; Wed, 30 Sep 2026 18:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790791248; cv=none; b=R57kKnhgmt8JVhfY05NNIplfn5hX29MPy5l2MlhzzmeqbeVxz3PbtFHSpxQoQgeIVm0tMqCi2YtftjsyyWS1zacJyym82cs1Kp7T+tNN3pzmF5M+aNpD5jy8qq2hI6MPo39mkZJzvEBIlU7e+Vs4Wb3CEOMt6hpbaq4GbbcWvyE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790791248; c=relaxed/simple; bh=WL1P/2dKYSdDI6YMAEbb1pcGYwV3Ut/rYAVeKqOM7D4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tSs7AZ2yAAzO/dRFcT8P7UDTmcL/1TeeZe/J1R4WfPQZV1MarZDbo6zee4y4TCkQx+Vbef8TJA0sCfgz+fj6OMM8tvHBc3XRZ4zQrwnSvyM5WaBmpY4JcjATm8iXDXt7yeXxCJlNeYi8pBMIbZPe96S2FQ/crkBkyIQG/bSamc0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Zk+7h1lh; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Zk+7h1lh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D39C1F000FF; Wed, 30 Sep 2026 18:00:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1790791247; bh=AQewhhKn/poVPlhqlUmqlTrtJrEXW59zuEWpbDOQP1M=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Zk+7h1lh+qBu71By5RAxPPXV/i1tNEVkLRYrvNuGPSSfB0ltgfStG0mqaCtec/Bb1 RELvg2t5w9KTy4oz4nSack3lwsjNUjMg7I0ujIeO+ysrbqbTAdY0FFdtaF2LiRdgnV MdF2FXucCMtyVSbabm0pjZbPtr6DBxqHb3mDqBsk= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Qiuxu Zhuo , Tony Luck , Sasha Levin Subject: [PATCH 5.15 236/752] EDAC/igen6: Fix channel selection hash Date: Wed, 30 Sep 2026 17:21:46 +0200 Message-ID: <20260930152403.373056112@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930152358.131179731@linuxfoundation.org> References: <20260930152358.131179731@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Qiuxu Zhuo [ Upstream commit 540b79536f3a89a66c5b6c490110298d43025618 ] In channel selection hash mode, the hardware decoding logic always includes the channel interleave bit in XOR operations. However, the hash mask may or may not include this channel interleave bit. When the mask does include this bit, the current igen6_edac code performs XOR on the interleave bit twice, effectively ignoring it - which is incorrect. Fix this issue by ensuring the hash mask always includes the interleave bit, so XOR is performed on the interleave bit exactly once. Fixes: 10590a9d4f23 ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC") Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Link: https://patch.msgid.link/20260730024238.4096623-4-qiuxu.zhuo@intel.com Signed-off-by: Sasha Levin --- drivers/edac/igen6_edac.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 8201e92714c68..d91b775173621 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -467,14 +467,22 @@ static enum mem_type get_memory_type(u32 mad_inter) static int decode_chan_idx(u64 addr, u64 mask, int intlv_bit) { - u64 hash_addr = addr & mask, hash = 0; - u64 intlv = (addr >> intlv_bit) & 1; + u64 hash_addr, hash = 0; int i; + /* + * In hash mode, the @intlv_bit is the lowest selected bit of @addr + * to be XORed. While @mask may or may not include this @intlv_bit, + * we enforce that @mask includes @intlv_bit to ensure @intlv_bit is + * XORed exactly once. + */ + mask |= 1 << intlv_bit; + hash_addr = addr & mask; + for (i = 6; i < 20; i++) hash ^= (hash_addr >> i) & 1; - return (int)hash ^ intlv; + return (int)hash; } static u64 decode_channel_addr(u64 addr, int intlv_bit) -- 2.53.0