From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D9015678C3; Wed, 30 Sep 2026 17:48:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790790501; cv=none; b=PkBBiQ9cFWGr4El8DisKAHt8i2V4Wk3a8rxNBFmoeId/15URM9ry70OaPhOqldR25uWqFBSwulFysgcuYKTm7EGXLOXI9NVHabhKJRVwz2r5bySc1F6SdGImfqVFBr6hIoOWeiK5KhlOgDGSmW7Ieq2j5o+G69ildqbVaoGGk0A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790790501; c=relaxed/simple; bh=ULuG8gT8U221VzuSF9n3Uf2t0X1QmUGVq488cdwPlvo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XZ7fpAE91U+G0E9nje12yoDCj58XEIWu358nO73yH0IYGzjicGvog1WssOLYNt7C8FYE3HcOewmlWQ451qC3Fd9Ux//gOC5DkrFvpx+922wNwUyTjMsOK45/i+nf3Id+jqFWh5c2DChPs2iI1nbbcRjnUkBLXP4B7NCIM4awIcg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=jGFN37wH; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="jGFN37wH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9F1E1F00898; Wed, 30 Sep 2026 17:48:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1790790500; bh=dcKE19HaO6jQ/X0RaAF8KAe3pVzr1OLZIp1IITABT3w=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=jGFN37wH75a8sK4F5tGq1ijR0fC+78FpaAu0kAY1S52IbvXfmAshms4KgW8tQzy9e O9D+V+l84A7q934dAc3Xjx2dColjCRR6nvBhWhwNhHlNbW+8DtxveHSKN112TD1J1h wn3zcrPyEaN53QQSeDdb6Bw6EI56qlq2dsLV7sBU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dapeng Mi , "Peter Zijlstra (Intel)" , Ingo Molnar , Sasha Levin Subject: [PATCH 6.12 851/877] perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification Date: Wed, 30 Sep 2026 17:29:22 +0200 Message-ID: <20260930152433.104013491@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930152414.738996857@linuxfoundation.org> References: <20260930152414.738996857@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Dapeng Mi [ Upstream commit 89dc568e8c0be60e05e5fcd0b528c79077d7b84b ] On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events. The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs. Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for: - MEM_UOPS_RETIRED.LOAD_LATENCY - MEM_UOPS_RETIRED.STORE_LATENCY Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction. This fixes incorrect STORE sample classification. Fixes: 39a41278f041 ("perf/x86/intel: Fix PEBS memory access info encoding for ADL") Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Cc: # v7.2+ Link: https://patch.msgid.link/20260917015234.981153-2-dapeng1.mi@linux.intel.com Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/intel/ds.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -303,6 +303,7 @@ static inline void pebs_set_tlb_lock(u64 static u64 __grt_latency_data(struct perf_event *event, u64 status, u8 dse, bool tlb, bool lock, bool blk) { + union perf_mem_data_src src; u64 val; WARN_ON_ONCE(is_hybrid() && @@ -318,7 +319,16 @@ static u64 __grt_latency_data(struct per else val |= P(BLK, NA); - return val; + src.val = val; + + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW)) + src.mem_op = P(OP, LOAD); + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW)) + src.mem_op = P(OP, STORE); + + return src.val; } u64 grt_latency_data(struct perf_event *event, u64 status) @@ -985,8 +995,8 @@ struct event_constraint intel_glm_pebs_e struct event_constraint intel_grt_pebs_event_constraints[] = { /* Allow all events as PEBS with no flags */ - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), - INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0x3f), + INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3), + INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0x3f), EVENT_CONSTRAINT_END };