From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F11EA50EC06; Wed, 30 Sep 2026 16:43:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790786601; cv=none; b=a7EWlUJqokB/BYc9tmISqP+9yabux289Bt/+Q3wIW6+oesUXs7dRQG0enW3XrK6vWDWhgBZJ/nANEXG1rsGB7azw6ZRXrvtpzGvjXhQKhRxGw1GFQI6UnBwXCxWDNJwEk7SadxwDZZx9lhkLfvw9toxbFY9ziWIc1+oFOZbd6so= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790786601; c=relaxed/simple; bh=yIj378vhj5OzM3hohZdYhlCeE2TrKAK/r27vWtw6hvA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XWH9NFulYpxNK4biNpPMlbpE5ZU2WXLy1qx3RwojGB5LrK2bHltMo0wsBxM7+1jPef3WmB/7PkQxyLlBvui/JiSR+qAcbQe8H5cLi2UwZG8GAfQ8fBl7rvBXsPTuhHwFfrH2hqdZcgTOz3lkdfROGOMyrAX++HtGHBU7b5k4HTw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=0ikKg+ds; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="0ikKg+ds" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5692D1F00893; Wed, 30 Sep 2026 16:43:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1790786599; bh=iQIFODp7l5oKNaoosA4UtemA3F5yGc+4nODE+mYJVfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=0ikKg+dswJVrqBcsrCeZYEXXWsLGypRQeTdBdcs4xeWjyyihYRc8zPqySjjewMGd/ Q7VN60t54gJobPQHiBN0UOCn3hWG2+desM3KxuZu0oR3fIQ5E5WkBNfr9+21D1WVMb I2jeRuuyUeOdFaoJ1a267agNmt8g3/1yBdfeWCqo= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Sean Christopherson , "Peter Zijlstra (Intel)" , Ingo Molnar , Dapeng Mi , Sasha Levin Subject: [PATCH 6.1 917/982] perf/x86/intel: Ensure KVM guest PEBS path doesnt set unwanted PERF_GLOBAL_CTRL bits Date: Wed, 30 Sep 2026 17:27:33 +0200 Message-ID: <20260930152436.436085955@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930152416.775402466@linuxfoundation.org> References: <20260930152416.775402466@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sean Christopherson [ Upstream commit cec38d5c098a350dcf084d345025136ade7e6d1e ] When reinstating PEBS counters into PERF_GLOBAL_CTRL for a KVM guest, mask the value with perf's desired/original PERF_GLOBAL_CTRL value to ensure KVM doesn't unintentionally set reserved bits in PERF_GLOBAL_CTRL. E.g. if the guest's PEBS_ENABLE value had bit 63, "Enable Precise Store", set, then using the raw guest PEBS value would propagate bit 63 to the guest's PERF_GLOBAL_CTRL value (which thankfully would be a failed VM-Entry, not a VMX Abort). The only reason this bug isn't reachable is because KVM doesn't support "Enable Precise Store" (which is probably a KVM bug?), i.e. bit 63 can't be set in kvm_pmu->pebs_enable and thus not in arr[pebs_enable].guest. In other words, this _should_ be a glorified NOP in the current code base. Fixes: c59a1f106f5c ("KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS") Signed-off-by: Sean Christopherson Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Reviewed-by: Dapeng Mi Link: https://patch.msgid.link/20260921191418.950933-2-seanjc@google.com Signed-off-by: Sasha Levin --- arch/x86/events/intel/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b1bc81bef4083..ac4e149af80c2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4190,7 +4190,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ - arr[global_ctrl].guest |= arr[pebs_enable].guest; + arr[global_ctrl].guest |= intel_ctrl & arr[pebs_enable].guest; } return arr; -- 2.53.0