From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 536D53AFAE2; Wed, 30 Sep 2026 19:21:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790796067; cv=none; b=aJsClCRjuEqUOjUXICIjfna9CZgr7H1LBGjnk3a66xfcX+i3j8Xess4yMgM8wGhgswqfSQDvIORP41OxW21f0anaAyWCULH62Zj8QYWHXW2DXQAIl6OrnQPoKnpDnZqlFM9PS+2Ejz0vzpmp9AE/npEDwEYR67fzeVwpPnY2gi0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790796067; c=relaxed/simple; bh=bLVxDqQr4febbwb/wPA6uRbofK94nKvZNbb0lMAYnEY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sOEaLZM0oClG0EDMzicl5eye2YRVm0BjyZ1Z/sVg04l+5Z3DGM8LufhgcLxQ7CWLAiqoRTB7x1N2DawX9pv5gPOT2LgfpqQtRSupkJ0s6U8GVaLdhhzmFic7CfSQHHpR/IHMfFnK25nHmfEWmNZ1k6OgBRlI8gteVbQuMwF9Lk4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=HjRk7r3u; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="HjRk7r3u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 791FC1F000FF; Wed, 30 Sep 2026 19:21:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1790796066; bh=teHTHRTbd8VcfLDgg4oKcFCstYD39PFThUy+CsgCtQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HjRk7r3ucC/Kfj2dGfBI1zW0krVpu7Yz3PMO5U3En9y4bozL6NnDi76Xzb/hO7iHA Q/BVfccvApfJJ7ZN1S392/p5JSDmIz1KgZGREDblYU7wPBhbUiOz1DTSn8w83jK/Oa ydDwAUWoF9qpmNekjpoM6jiD0dl2T9ds1i+zsBcY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Manivannan Sadhasivam , AngeloGioacchino Del Regno , Vinod Koul , Sasha Levin Subject: [PATCH 6.6 0782/1193] phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow Date: Wed, 30 Sep 2026 17:24:26 +0200 Message-ID: <20260930152451.624181365@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930152434.301151190@linuxfoundation.org> References: <20260930152434.301151190@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: AngeloGioacchino Del Regno [ Upstream commit de7f29a1fe1dc2864d8a47f8c39d508442cae167 ] When trying to calculate a PLL rate for target display resolutions above 2560x1440, 24bpp, 30Hz, the pixel clock value will be more than 32-bits long but the division to finally calculate the digital clock divider is being done with div_u64(), which expects a 32bit unsigned divisor. Fix the overflow by using div64_u64() instead. Fixes: 9d9ff3d2a4a5 ("phy: mediatek: hdmi: mt8195: fix wrong pll calculus") Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno Link: https://patch.msgid.link/20260911074015.9994-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index bbfe11d6a69d7..80600b2b6b38d 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -288,7 +288,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, posdiv2 = 1; /* Digital clk divider, max /32 */ - digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); + digital_div = div64_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <= 32 && digital_div >= 1)) return -EINVAL; -- 2.53.0