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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36741f753f7sm8840346eec.27.2026.10.21.10.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 10:43:41 -0700 (PDT) Date: Wed, 21 Oct 2026 10:43:36 -0700 From: Jonathan Cameron To: Jason Gunthorpe Cc: Alexandre Ghiti , Albert Ou , Ard Biesheuvel , Arnd Bergmann , Catalin Marinas , Jonathan Corbet , David Sterba , Ilias Apalodimas , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Randy Dunlap , Simon Glass , Shuah Khan , Nick Terrell , Will Deacon , Alexandre Ghiti , Conor Dooley , linux-integrity@vger.kernel.org, Palmer Dabbelt , patches@lists.linux.dev, Piotr =?ISO-8859-1?Q?Kr=F3l?= , Ross Philipson , Sami Tolvanen , Song Shuai Subject: Re: [PATCH v2 11/15] arm64: drtm: Add macro definitions for DEN0113 Message-ID: <20261021104336.00000437@oss.qualcomm.com> In-Reply-To: <11-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> References: <0-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> <11-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=S8ZMU4sP c=1 sm=1 tr=0 ts=6ad8f9cf cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=Ikd4Dj_1AAAA:8 a=EUspDBNiAAAA:8 a=cBdanpMcOxUnX1AP4g8A:9 a=CjuIK1q_8ugA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: N8CRGGSTzDZsB93YMklYNuiHE2Oa0AmH X-Proofpoint-GUID: N8CRGGSTzDZsB93YMklYNuiHE2Oa0AmH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA3MCBTYWx0ZWRfX0NlwWYDfNgGS 9qh4CVYMH0rD8b1SgL5GWsX1oxtTH7yTygmExpNf1Pt/sACtlb9plP5U27bmIhnDxaoQFFCIpRB xRzYFZoR6e3LoOLe0FpJWP7umLy/3Nw2RdaCmU2mQT5YFEC30HE3uPVcO+LyX+m9+2YMPbKLshr x9SopRYGJzytmbrg2luWh7+RSuL9b4xyLDF3POfikqtKk48OIfCjmLR1Fq8G/J2evPYG9kK7Oac yjZshDrVFNo4vrtQgOK6VDMKhuAQvttKYivFaWHbQRDTLVx3yaMcx+hXgLr8WHuDdjeR60sN0HT C2QOyDrsCVg2GSecwCudoXjDJpZkBYLW9Zy8cVQbx73dcqBFo/Z8uIVHam/sSxwBpeLCZVGBvn6 ASVTI+Z1sHRs9uaTS7Ta8rvrwD3BeDgH6GI/Xhe2loxHgTgXtdNUpEufM5JOWlUlHcM1PN7YKkf cZ4xI0LxVB7y4v8a37Q== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA3MCBTYWx0ZWRfX72Mb/HzGKdhZ 9F9Yff1Vrpewc9qES5cA6qRa6+D+Hp94Fb1Zf94m4dXwJQitnJa5+Wp0JTMV0pDeztPEWLZMle9 0YMj5ZuwGZqUWq3wjQN14Cyn4Os+Nrg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_04,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210070 On Fri, 2 Oct 2026 20:31:48 -0300 Jason Gunthorpe wrote: > Taken from rev 1.4b of the spec, following the SMCC register layout and > constant names. > > Signed-off-by: Jason Gunthorpe Nice - appreciated the spec references as saved a bunch of searching. A few really small comments inline. Either way Reviewed-by: Jonathan Cameron > --- > arch/arm64/include/asm/drtm.h | 304 ++++++++++++++++++++++++++++++++++ > 1 file changed, 304 insertions(+) > create mode 100644 arch/arm64/include/asm/drtm.h > > diff --git a/arch/arm64/include/asm/drtm.h b/arch/arm64/include/asm/drtm.h > new file mode 100644 > index 00000000000000..8188af1b582bb3 > --- /dev/null > +++ b/arch/arm64/include/asm/drtm.h > +/* > + * The spec uses 4KB pages for sizes and alignment throughout, see v1.4B > + * sections 3.3, 3.13, 3.14 and 3.15. > + */ > +#define ARM_DRTM_PAGE_SIZE 4096 Maybe use SZ_4K from linux/sizes.h > +/* v1.4B section 3.3 "DRTM_FEATURES" */ > +#define ARM_DRTM_SMC_FEATURES (ARM_DRTM_SMC_FN_BASE + 0x01) > +/* X1 input parameter */ > +#define ARM_DRTM_FEATURE_SELECTOR BIT_U64(63) Maybe define the alternate masking for function ID - for completeness if nothing else. > +#define ARM_DRTM_FEATURE_ID_MASK GENMASK_U64(7, 0) > +/* > + * PCR schema numbers. ARM_DRTM_PCR_SCHEMA_MASK is a bitmap indexed by these, > + * and the Launch Features ARM_DRTM_LAUNCH_PCR_SCHEMA_MASK field holds one. > + */ Similar to below. Maybe this dual use is a bit fragile. > +#define ARM_DRTM_PCR_SCHEMA_DEFAULT 0 > +#define ARM_DRTM_PCR_SCHEMA_AUTHORITIES 1 > +/* v1.4B Table 6 "DMA protection features" */ > +#define ARM_DRTM_FEATURE_DMA_PROTECTION 0x03 > +#define ARM_DRTM_DMA_PROTECTION_MASK GENMASK_U64(7, 0) > +/* Only valid if ARM_DRTM_DMA_PROTECTION_REGION is supported */ > +#define ARM_DRTM_MAX_REGIONS_MASK GENMASK_U64(23, 8) > + > +/* > + * DMA protection types. ARM_DRTM_DMA_PROTECTION_MASK is a bitmap indexed by > + * these, and the Launch Features ARM_DRTM_LAUNCH_DMA_PROTECTION_MASK field > + * holds one. > + */ > +#define ARM_DRTM_DMA_PROTECTION_COMPLETE 0 > +#define ARM_DRTM_DMA_PROTECTION_REGION 1 The dual use of these for bitmap indexes in one place and values in another seems fragile. Maybe it is better to have different naming for the two even though the values match? > +/* v1.4B section 3.4 "DRTM_DYNAMIC_LAUNCH" */ > +#define ARM_DRTM_SMC_DYNAMIC_LAUNCH (ARM_DRTM_SMC_FN_BASE + 0x04) > + > +/* v1.4B section 3.5 "DRTM_UNPROTECT_MEMORY" */ > +#define ARM_DRTM_SMC_UNPROTECT_MEMORY (ARM_DRTM_SMC_FN_BASE + 0x03) > + > +/* v1.4B section 3.6 "DRTM_CLOSE_LOCALITY" */ > +#define ARM_DRTM_SMC_CLOSE_LOCALITY (ARM_DRTM_SMC_FN_BASE + 0x05) > + > +/* v1.4B section 3.7 "DRTM_GET_ERROR" */ > +#define ARM_DRTM_SMC_GET_ERROR (ARM_DRTM_SMC_FN_BASE + 0x06) > + > +/* v1.4B section 3.8 "DRTM_SET_ERROR" */ I know I'm the one who asks for references, but maybe the SMC numbers are obvious enough without given the name matches the spec section? The table references etc below are excellent! The do no harm beyond a bit of bloat though so I don't mind if you want to keep them. > +#define ARM_DRTM_SMC_SET_ERROR (ARM_DRTM_SMC_FN_BASE + 0x07) > + > +/* v1.4B Table 8 "Definition for error IDs (Bits[10:3])" */ > +#define ARM_DRTM_ERROR_ID_NONE 0x0 > +#define ARM_DRTM_ERROR_ID_PARAMETERS 0x2 > +#define ARM_DRTM_ERROR_ID_SECURE_EXCEPTION 0x3 > +#define ARM_DRTM_ERROR_ID_TCB_HASH_UNLOCKED 0x4 I'd use NOT_LOCKED to align with spec. Maybe it makes a subtle difference somewhere? UNLOCKED might imply a transition to that state, where as NOT_LOCKED doesn't. Meh, doesn't really matter as I'm probably over thinking this. > +#define ARM_DRTM_ERROR_ID_TPM 0x5 > +#define ARM_DRTM_ERROR_ID_SIGNATURE 0x6 > +#define ARM_DRTM_ERROR_ID_IMAGE_FORMAT 0x7 > +#define ARM_DRTM_ERROR_ID_VENDOR 0xFF > +/* > + * v1.4b Section 3.3.1 says: > + * A return value of greater than 0 means the feature ID is > + * implemented, and there are other feature-specific > + * feature or capability bits available in other return value > + * registers. I'd wrap to 80 chars. > + * And for FEATURE_SELECTOR all defined features return data in other > + * registers, so 0 is not an allowed return. > + */ > +static inline s64 arm_drtm_query_feature(u64 feature, u64 *value) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_1_1_smc(ARM_DRTM_SMC_FEATURES, > + ARM_DRTM_FEATURE_SELECTOR | > + FIELD_PREP(ARM_DRTM_FEATURE_ID_MASK, feature), > + 0, 0, 0, 0, 0, 0, &res); > + *value = res.a1; > + return res.a0; > +} > + > +#endif /* !__ASSEMBLY__ */ > +#endif /* __ASM_DRTM_H */