From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793211203; b=bxOVCxxRqkc+Lakz8AgM/wZLicl+pdKrJAVuQpNsSvPsXJElV+J9Vl4jHSiUTNNNZT3w lruGa9NM0HQNmH1r/sf63K9QLiZX1LNjYCfjw89iyGZzHia8Snwkhaq54EOML/TfZZz/W Pn5V2eDWQd03TU5qu8+/FyADgTUjD4j+6RYlaK1omz9ksJXfalZMPpMT4qIlbHgzIzcjg f5wmAF3S9knwsZuCz0pVQ5a8fRF2+qeFWAOdaNJLNF2iXlDvPrShF3xZtDqiR0fycEJ1Q /kx8YxQ3XDAEruBLSvOYKYWroVQDyRkzg+wk57PpX+08HZiUuDripRdXTpiyp7iqo0Q== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793211203; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=/Dj4CiheR5dFzLCxk6wb+Dd8vENlwifpdI8zmmeQfK4=; b=gbLPqyaFRpZDUC/l7vM/ywVGn/yM1KkSQ5aVFPmGmDwlZ+/FpSsJfLOdW5zDOHsJafkm 28aNP1uphzcA+MQ/QmJCB73k2Nl7wmsK0jL+53ewGSLtehKd07WGdyX428LIa4AXgSvHF 3rNGwBplDy06FVCZu8VnCPK2RdsLnpct6mFUX6hOiVCIhr5jGg4o5NBhUmPjmdXYm0brZ HdKvEUzb63PUnj+V0bWQShxv+bxzJW4g3zFg28udby8Peni7GxfqU750+5D/G047uMxMl Lysf0Ns838LN0UkIsJfYthaYZ4gxyYs7/+Yy7wxQUIluF3LBGqpleXDDnBniP0g994Q== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=WRXw+PmE; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06F72606A952; Wed, 28 Oct 2026 18:13:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=WRXw+PmE Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54EAB1F01825; Wed, 28 Oct 2026 18:13:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1793211202; bh=/Dj4CiheR5dFzLCxk6wb+Dd8vENlwifpdI8zmmeQfK4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WRXw+PmEWx4GI/EQfcGKsYLz62VqxgVWfErr7UPSFeZdIgxiQR/1dFU7XcLnSAh0N Zh5H0+FDNH17pTqzyl07+PScYKjfmnMBLu0qUKwcD6daLJKI+u12/MaUrOgBkWD7YU rxaa2ALu4Lhg/eOIONmiGD1Fu36DsMQbtE9V3H5I= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Beata Michalska , Vladimir Murzin , Will Deacon , Sasha Levin Subject: [PATCH 5.15 295/571] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Date: Wed, 28 Oct 2026 17:57:22 +0100 Message-ID: <20261028170014.999845929@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261028170008.009143722@linuxfoundation.org> References: <20261028170008.009143722@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Beata Michalska [ Upstream commit 45f7304679875eb000d67e194090ee7abd05c89c ] Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency. The AMEVCNTR01_EL0 counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source. The erratum can also affect PMUv3 users of the CNT_CYCLES event, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround. Cc: stable@vger.kernel.org Signed-off-by: Beata Michalska Reviewed-by: Vladimir Murzin Signed-off-by: Will Deacon Signed-off-by: Beata Michalska Signed-off-by: Sasha Levin --- Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 22 ++++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 4 ++++ arch/arm64/kernel/topology.c | 9 +++++---- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index b2590a08c711c..73dff0057b257 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -138,6 +138,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 27b5ef31e471d..3e617076128d6 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -741,6 +741,28 @@ config ARM64_ERRATUM_2457168 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE bool diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 6da777e815d6b..0529d0e5bdf52 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -264,6 +264,10 @@ static const struct midr_range workaround_amu_constcnt_list[] = { #ifdef CONFIG_ARM64_ERRATUM_2457168 /* Cortex-A510 r0p0-r1p1 */ MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 + /* Cortex-A725 r0p0 - r0p2 */ + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), #endif {} }; diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 615efd611a873..b142254d8c0fb 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -280,10 +280,11 @@ static void cpu_read_corecnt(void *val) static void cpu_read_constcnt(void *val) { /* - * Return 0 if the current CPU is affected by erratum 2457168. A value - * of 0 is also returned if the current CPU does not support AMUs or if - * the counter is disabled. A return value of 0 at counter read is - * properly handled as an error case by the users of the counter. + * Return 0 if the current CPU is affected by a HW erratum. + * A value of 0 is also returned if the current CPU does not + * support AMUs or if the counter is disabled. A return + * value of 0 at counter read is properly handled as an error + * case by the users of the counter. */ *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); -- 2.53.0