From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793212555; b=l/01R4DMOtCxJ8Yd+4T8oj4Bn/ESG7yJSLhjLsAyutT0910CLc9k3JCE/qmqQUmsXYix eWCtlqUc3SpBwSkJ5QnCaqgB1YGSXTV+K+7maH6BC1oQhw2V8wOQPRjBRCtHVWQfJhijc xenN3B5m4e0HqsORQ+jIfKI0r6up6m9wN5oAY2B8mSPxiRa49NGCT8bhwVQMKtHfsjr87 7hHuN3uyypP0zXxThuAFjZ6wGQAsSjsiB4UTRknOhb8Z1Ip6xFPVERdgS/dN42W/3dy8P hKjD7BLVqpW+bukjRhzCwt/RMcEJ4pa0p5vPz+KbVMt5jAftIuxT/iPGipp4+1L3rIw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793212555; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=1TXDYU/CeEBngu1BRrsvVVmv/9NXQmkDsu/aQ9+qLjA=; b=D8hXc6x56s/GrlG5Ze2DqXsd+P7kJQNTkZ0P7mu4k4hjQfU9XsrXOsdOq11kPGbbpIEb KzkJl238ihkXAHTFBOyql0mEIJ2zV0rjbTEcNo4a+Xxi+PgqpxyvI2/qBGMAgDuN9oc/U Q38glbi0LufyJdj1SR3nJbGlHRr2r23KWtdM3mM076Xb9wtayZvTx1RAhoy7UpdyNePgs QmB+1jkdwUpmDkl4qrj5qTLEIFcYhSKxUyuEDn+6nZg4sOXe0eFfd3hCQe+E3ciVxAgH/ rzxcpne+orgwVy7p6q924JQUHfV7YW7mhiMGDAqnobD5l2Fy7XfbxAamK5FKVAILQ6g== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=KLAzZjFT; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8779A606A31A; Wed, 28 Oct 2026 18:35:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=KLAzZjFT Received: by smtp.kernel.org (Postfix) with ESMTPSA id D6DB31F01825; Wed, 28 Oct 2026 18:35:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1793212555; bh=1TXDYU/CeEBngu1BRrsvVVmv/9NXQmkDsu/aQ9+qLjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KLAzZjFT9fm2x53cd3HWlKtZrVMFaEZ6ClebaltQxehvVT9vofsXZACBK5Wjpn2DJ eVOApimFuIX+wuVqkHKuZ2Sx661nq+9BFmJSW91Tbgnrg8dwgVoLLFJ9y3cF1yetfr ijBlxiEVe58BHGlLUSchdz18xYWl3DuM6iJsEITc= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dapeng Mi , "Peter Zijlstra (Intel)" , Ingo Molnar , Sasha Levin Subject: [PATCH 6.1 0158/1887] perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification Date: Wed, 28 Oct 2026 17:37:34 +0100 Message-ID: <20261028170502.829844552@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261028170459.200466217@linuxfoundation.org> References: <20261028170459.200466217@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Dapeng Mi [ Upstream commit 89dc568e8c0be60e05e5fcd0b528c79077d7b84b ] On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events. The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs. Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for: - MEM_UOPS_RETIRED.LOAD_LATENCY - MEM_UOPS_RETIRED.STORE_LATENCY Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction. This fixes incorrect STORE sample classification. Fixes: 39a41278f041 ("perf/x86/intel: Fix PEBS memory access info encoding for ADL") Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Cc: # v7.2+ Link: https://patch.msgid.link/20260917015234.981153-2-dapeng1.mi@linux.intel.com Signed-off-by: Sasha Levin --- arch/x86/events/intel/ds.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index d1cf9876c931d..d05db7aeef78a 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -224,6 +224,7 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock) static u64 __grt_latency_data(struct perf_event *event, u64 status, u8 dse, bool tlb, bool lock, bool blk) { + union perf_mem_data_src src; u64 val; WARN_ON_ONCE(is_hybrid() && @@ -238,7 +239,16 @@ static u64 __grt_latency_data(struct perf_event *event, u64 status, else val |= P(BLK, NA); - return val; + src.val = val; + + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW)) + src.mem_op = P(OP, LOAD); + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW)) + src.mem_op = P(OP, STORE); + + return src.val; } u64 grt_latency_data(struct perf_event *event, u64 status) @@ -839,8 +849,8 @@ struct event_constraint intel_glm_pebs_event_constraints[] = { struct event_constraint intel_grt_pebs_event_constraints[] = { /* Allow all events as PEBS with no flags */ - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), - INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0x3f), + INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3), + INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0x3f), EVENT_CONSTRAINT_END }; -- 2.53.0