From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794591032; b=48LeAYh1w4rFM3a+FXKkyMTxCb9hKg1KVe5OvU8vB5/F+gUuCrz6A2H7hfgvl5Gt7Pmq xs4xpoMsnrsiItcGEwunsNClJpPUrQFhSKgP02AoKFNShFr7RcNBxzRnnenFPMlODmLQi jP5w2y+RL4SlVrmcAiym5G2VPcu/DnQ8BeclmvoodKXJ3AMMU2iKkztY29RqaHp9lFtJy sjd5gWD/apVoozfqMXpaUQJGpCMcHBKpraZ1r7Qsg7UkM33l9HBUw73XQrpGdeGt2F2p/ 9eNnYkEaKkOOcbim2OmbsVZfiQSTL75SMsEHTiRqrj3wS8jQ81InW1evv14QyVzBJZQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794591032; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=YHtYJ3nOY/prXNUYE1B2GT/hzwO+I28BTl67jr3GEvk=; b=R1RYd7y3xhhfotSN6FO/f4HjDnDdltPUEHu4sXEMQLacK4gbwE/9V+pPRhYA/+jSmtip 0N2Y35sZJ/AkgZ5jq8MnrZSZ/q8oClIb6REKZ2X9QQYE7A5JJWot6+6XuIesUE7ubqIoi +Vmp6plsNbZOPo/PaxA6FNTQjVYHbges61hvBix8cDJ7oNEe5emukv+HTaQsXmPwdqBRm V1x+LOaH6y3auDQJSAzaTo1Fx3vVqq+5MnKSpJz3xE0nLt+6FdgKvWDNl3OyqvQoBQm3K msEp+eQ4dBrO6c6x9Rvr7NBZ60wDIoef+6XysO2lJKM0HQhB5AVbtEo4v41odiPzcEw== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=C6DXzmj3; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B02960703E9; Fri, 13 Nov 2026 17:30:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=C6DXzmj3 Received: by smtp.kernel.org (Postfix) with ESMTPSA id C54DF1F000C8; Fri, 13 Nov 2026 17:30:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1794591032; bh=YHtYJ3nOY/prXNUYE1B2GT/hzwO+I28BTl67jr3GEvk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=C6DXzmj3oR+vWbjsmI/mF2d6oo6RMVkkbUYN4oyD1ARcSpImieCAMASjTJjNsrnPQ jhmzZP3oawIkMFgh/QrDh9g0peQRDAANBBQaa4dtTOcR/ARRT2wqQ9olr46vWphcyt MQAiteUR0HhFFNpm41pynf+b2u//GM9zmZoOLd0c= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Eugen Hristev , Balakrishnan Sambath , Hans Verkuil , Sasha Levin Subject: [PATCH 6.12 143/670] media: microchip-isc: fix WB offset and gain register field masking Date: Fri, 13 Nov 2026 10:45:07 -0500 Message-ID: <20261113153816.729532629@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261113153811.177190860@linuxfoundation.org> References: <20261113153811.177190860@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Balakrishnan Sambath [ Upstream commit 6e9eaa3b93870e4edac1bd2539fe113c24663eaf ] ISC_WB_O_* and ISC_WB_G_* each pack two 13-bit fields. A negative offset sign-extends and corrupts the adjacent field. Add masks for the two fields and write them with FIELD_PREP(), which masks each value into its field, so sign extension can no longer bleed across. Fixes: 73c1a577b839 ("media: atmel: atmel-isc: reworked white balance feature") Cc: stable@vger.kernel.org Reviewed-by: Eugen Hristev Signed-off-by: Balakrishnan Sambath Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- .../platform/microchip/microchip-isc-base.c | 16 ++++++++-------- .../platform/microchip/microchip-isc-regs.h | 6 ++++++ 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/drivers/media/platform/microchip/microchip-isc-base.c index 97cd1f74ff2b9..3d09c421f370e 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -62,17 +62,17 @@ static inline void isc_update_awb_ctrls(struct isc_device *isc) /* In here we set our actual hw pipeline config */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + FIELD_PREP(ISC_WB_O_LO, ctrls->offset[ISC_HIS_CFG_MODE_R]) | + FIELD_PREP(ISC_WB_O_HI, ctrls->offset[ISC_HIS_CFG_MODE_GR])); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + FIELD_PREP(ISC_WB_O_LO, ctrls->offset[ISC_HIS_CFG_MODE_B]) | + FIELD_PREP(ISC_WB_O_HI, ctrls->offset[ISC_HIS_CFG_MODE_GB])); regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + FIELD_PREP(ISC_WB_G_LO, ctrls->gain[ISC_HIS_CFG_MODE_R]) | + FIELD_PREP(ISC_WB_G_HI, ctrls->gain[ISC_HIS_CFG_MODE_GR])); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); + FIELD_PREP(ISC_WB_G_LO, ctrls->gain[ISC_HIS_CFG_MODE_B]) | + FIELD_PREP(ISC_WB_G_HI, ctrls->gain[ISC_HIS_CFG_MODE_GB])); } static inline void isc_reset_awb_ctrls(struct isc_device *isc) diff --git a/drivers/media/platform/microchip/microchip-isc-regs.h b/drivers/media/platform/microchip/microchip-isc-regs.h index e77e1d9a1db87..166f57e6ed5d7 100644 --- a/drivers/media/platform/microchip/microchip-isc-regs.h +++ b/drivers/media/platform/microchip/microchip-isc-regs.h @@ -149,6 +149,12 @@ /* ISC White Balance Gain for B, GB Register */ #define ISC_WB_G_BGB 0x0000006c +/* Each WB offset/gain register packs two 13-bit fields, low and high */ +#define ISC_WB_O_LO GENMASK(12, 0) /* R or B offset [12:0] */ +#define ISC_WB_O_HI GENMASK(28, 16) /* GR or GB offset [28:16] */ +#define ISC_WB_G_LO GENMASK(12, 0) /* R or B gain [12:0] */ +#define ISC_WB_G_HI GENMASK(28, 16) /* GR or GB gain [28:16] */ + /* ISC Color Filter Array Control Register */ #define ISC_CFA_CTRL 0x00000070 -- 2.53.0