From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794591292; b=VYBSb7k9M32D5688nsp45S6I0LEbFuMN0AttzXHVR/pvwQ5Cz1WNGqp6QjvDnvA5egjO Ho590bc8gjHe8I4XYdpW+8zXbJxxP4BIftBNo1hk9xKAJnQ2JCCobm0eJ1jgdL2aALRuw SEo89SMFwVt5+6YUxGI0099xofJVphwKzs7C67SaD+eBOV/CT+pZvZUu5wpwt1qho/7yn ug4y9/qkh0EN0mRLOub3xBU2EXqTxSjA4NS8SEvIxCtDrYfztKFNjrAfM5Md/RgET9CaT Au9VnvZCGJ6tdt4eDd6g4xvb/N0N9rxay6tk0AB7BuY1PcMDezypwesQm37BHeiTgtw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794591292; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=PYSTS0ys+GCrU6uPMYBVwvtvqffDa496kzJ0rUgQokE=; b=Rm6g2BnNXIZxl+23n9hsZLgtq2crQGJBgBtHRXfz8qg0YG4NytrSkJ0cCDA27zApPuwr OG1yGoWd1wclyDIQViSVdUYHferQE0X/cb2m4B84/UDN+wMWsOgHql2va7Nup6RT1jy6H 8s0XCa4F73HPgYS3ZY2ICP9cPrv6hgS9uUfzdcuMvvyJxMPa8VzVKADpeLVc15Bg5n1tX e/+orjAyZRC0Mb/VGUxbtNhgG57yg8sWMFEYFHW5/dYKdfI//0dp0JBQkoSayNfkacD1R cDPsZ9ZQ9wMYEPNXR/P59hnG7YQgoqZ8xJw0jhb2n6BeVgmbIbuqRlOoVV/OOj7KzTA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=T3HJlpEk; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81B3A6077D4D; Fri, 13 Nov 2026 17:34:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=T3HJlpEk Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C5391F000C4; Fri, 13 Nov 2026 17:34:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1794591292; bh=PYSTS0ys+GCrU6uPMYBVwvtvqffDa496kzJ0rUgQokE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=T3HJlpEkpI21ypQWydHl0iBv/HW41stLfyHwzOFDuJv+ef/ytSX8rn6m/FcIb21nY fe7eEkYJ04qANSsmS+CEeKpL4/JPeUOIfypMbzm/j1WOguj90EjySsL6/dE1NKJZ5+ PIvJpB3bzSU3cVdKUEAbldfsEbSBLXY4706lUFDU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Imre Kaloz , Thomas Bogendoerfer , Sasha Levin Subject: [PATCH 6.12 383/670] MIPS: sgi-ip32: Mask MACE PCI interrupts in CRIME only Date: Fri, 13 Nov 2026 10:49:07 -0500 Message-ID: <20261113153824.751529814@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261113153811.177190860@linuxfoundation.org> References: <20261113153811.177190860@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Imre Kaloz [ Upstream commit 4e65c502b8975e7c3c3d84aba59cd04af1dd6b8a ] Masking PCI interrupts in the MACE PCI control register overwrites the error and arbitration enables set at init, and a read-modify-write can hang CRIME 1.1 machines under DMA load. Enable the slot interrupts once and mask them in CRIME. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: stable@vger.kernel.org Signed-off-by: Imre Kaloz Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/pci/pci-ip32.c | 7 ++++-- arch/mips/sgi-ip32/ip32-irq.c | 45 +++-------------------------------- 2 files changed, 8 insertions(+), 44 deletions(-) diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index 7ae89d0c70990..30aca6f76563d 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -125,10 +125,13 @@ static int __init mace_init(void) { PCIBIOS_MIN_IO = 0x1000; - /* Clear any outstanding errors and enable interrupts */ + /* + * Clear any outstanding errors and enable interrupts. PCI interrupts + * are masked in CRIME, so the per-slot enables stay on. + */ mace->pci.error_addr = 0; mace->pci.error = 0; - mace->pci.control = 0xff008500; + mace->pci.control = 0xff0085ff; printk("MACE PCI rev %d\n", mace->pci.rev); diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 29d04468a06b8..b9c72af481edb 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -160,38 +160,6 @@ static struct irq_chip crime_edge_interrupt = { .irq_unmask = crime_enable_irq, }; -/* - * This is for MACE PCI interrupts. We can decrease bus traffic by masking - * as close to the source as possible. This also means we can take the - * next chunk of the CRIME register in one piece. - */ - -static unsigned long macepci_mask; - -static void enable_macepci_irq(struct irq_data *d) -{ - macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ); - mace->pci.control = macepci_mask; - crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE); - crime->imask = crime_mask; -} - -static void disable_macepci_irq(struct irq_data *d) -{ - crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE)); - crime->imask = crime_mask; - flush_crime_bus(); - macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ); - mace->pci.control = macepci_mask; - flush_mace_bus(); -} - -static struct irq_chip ip32_macepci_interrupt = { - .name = "IP32 MACE PCI", - .irq_mask = disable_macepci_irq, - .irq_unmask = enable_macepci_irq, -}; - /* This is used for MACE ISA interrupts. That means bits 4-6 in the * CRIME register. */ @@ -299,8 +267,8 @@ static struct irq_chip ip32_maceisa_edge_interrupt = { .irq_unmask = enable_maceisa_irq, }; -/* This is used for regular non-ISA, non-PCI MACE interrupts. That means - * bits 0-3 and 7 in the CRIME register. +/* This is used for regular non-ISA MACE interrupts. That means bits 0-3 + * and 7-15 in the CRIME register. */ static void enable_mace_irq(struct irq_data *d) @@ -436,20 +404,13 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { switch (irq) { - case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: + case MACE_VID_IN1_IRQ ... MACEPCI_SHARED2_IRQ: irq_set_chip_and_handler_name(irq, &ip32_mace_interrupt, handle_level_irq, "level"); break; - case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: - irq_set_chip_and_handler_name(irq, - &ip32_macepci_interrupt, - handle_level_irq, - "level"); - break; - case CRIME_CPUERR_IRQ: case CRIME_MEMERR_IRQ: irq_set_chip_and_handler_name(irq, -- 2.53.0