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b=IeRcM7nfLVlxUhzbSNPMxE+D9lAKD6yxKbjvBHr1S0MoCEOhxZZeklEfdkwRptrvCbwjlpjfh2CxBFr3xKYTfDdKcs3QyxL9XCJ8fQB8Zk3z7y3S16ulI/vqaN/QtH31JfVI08zll9E780oi12oF2WKganfSg7cjICYOE28sYps= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS7PR12MB6048.namprd12.prod.outlook.com (2603:10b6:8:9f::5) by SN7PR12MB8789.namprd12.prod.outlook.com (2603:10b6:806:34b::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9203.10; Thu, 9 Oct 2025 11:44:19 +0000 Received: from DS7PR12MB6048.namprd12.prod.outlook.com ([fe80::6318:26e5:357a:74a5]) by DS7PR12MB6048.namprd12.prod.outlook.com ([fe80::6318:26e5:357a:74a5%7]) with mapi id 15.20.9203.007; Thu, 9 Oct 2025 11:44:18 +0000 Message-ID: <23116fce-b71c-46fe-a7a0-c2a01a7592f1@amd.com> Date: Thu, 9 Oct 2025 17:14:04 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 04/15] iommupt: Add the AMD IOMMU v1 page table format To: Jason Gunthorpe Cc: Jonathan Corbet , iommu@lists.linux.dev, Joerg Roedel , Justin Stitt , Kevin Tian , linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, llvm@lists.linux.dev, Bill Wendling , Nathan Chancellor , Nick Desaulniers , Miguel Ojeda , Robin Murphy , Shuah Khan , Suravee Suthikulpanit , Will Deacon , Alexey Kardashevskiy , Alejandro Jimenez , James Gowans , Michael Roth , Pasha Tatashin , patches@lists.linux.dev References: <4-v5-116c4948af3d+68091-iommu_pt_jgg@nvidia.com> <4f50b0f3-c62d-452d-9a39-5c47ac201d01@amd.com> <20251008130813.GB3765120@nvidia.com> Content-Language: en-US From: Vasant Hegde In-Reply-To: <20251008130813.GB3765120@nvidia.com> Content-Type: text/plain; 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Unlike other x86 page tables >>> this explicitly does not do sign extension as part of allowing the entire >>> 64 bit VA space to be supported. >> >> I am still catching up w/ entire series.. But here is few fixes needed to boot >> this series w/ SME. > > I got them all, like this - thanks a lot! Looks good. Thanks! -Vasant > > diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c > index 92095fd17b3899..0b97db94c8c4e0 100644 > --- a/drivers/iommu/amd/iommu.c > +++ b/drivers/iommu/amd/iommu.c > @@ -2054,7 +2054,7 @@ static void set_dte_entry(struct amd_iommu *iommu, > &pt_info); > } > > - new.data[0] |= pt_info.host_pt_root | > + new.data[0] |= __sme_set(pt_info.host_pt_root) | > (pt_info.mode & DEV_ENTRY_MODE_MASK) > << DEV_ENTRY_MODE_SHIFT; > } > @@ -2166,7 +2166,7 @@ static int init_gcr3_table(struct iommu_dev_data *dev_data, > return ret; > > pt_iommu_x86_64_hw_info(&pdom->amdv2, &pt_info); > - ret = update_gcr3(dev_data, 0, pt_info.gcr3_pt, true); > + ret = update_gcr3(dev_data, 0, __sme_set(pt_info.gcr3_pt), true); > if (ret) > free_gcr3_table(&dev_data->gcr3_info); > > diff --git a/drivers/iommu/generic_pt/fmt/amdv1.h b/drivers/iommu/generic_pt/fmt/amdv1.h > index d7660d4170ef78..26e29b08a9b4ae 100644 > --- a/drivers/iommu/generic_pt/fmt/amdv1.h > +++ b/drivers/iommu/generic_pt/fmt/amdv1.h > @@ -73,22 +73,29 @@ enum { > > static inline pt_oaddr_t amdv1pt_table_pa(const struct pt_state *pts) > { > - return oalog2_mul(FIELD_GET(AMDV1PT_FMT_OA, pts->entry), > - PT_GRANULE_LG2SZ); > + u64 entry = pts->entry; > + > + if (pts_feature(pts, PT_FEAT_AMDV1_ENCRYPT_TABLES)) > + entry = __sme_clr(entry); > + return oalog2_mul(FIELD_GET(AMDV1PT_FMT_OA, entry), PT_GRANULE_LG2SZ); > } > #define pt_table_pa amdv1pt_table_pa > > /* Returns the oa for the start of the contiguous entry */ > static inline pt_oaddr_t amdv1pt_entry_oa(const struct pt_state *pts) > { > - pt_oaddr_t oa = FIELD_GET(AMDV1PT_FMT_OA, pts->entry); > + u64 entry = pts->entry; > + pt_oaddr_t oa; > > - if (FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, pts->entry) == > - AMDV1PT_FMT_NL_SIZE) { > + if (pts_feature(pts, PT_FEAT_AMDV1_ENCRYPT_TABLES)) > + entry = __sme_clr(entry); > + oa = FIELD_GET(AMDV1PT_FMT_OA, entry); > + > + if (FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, entry) == AMDV1PT_FMT_NL_SIZE) { > unsigned int sz_bits = oaffz(oa); > > oa = oalog2_set_mod(oa, 0, sz_bits); > - } else if (PT_WARN_ON(FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, pts->entry) != > + } else if (PT_WARN_ON(FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, entry) != > AMDV1PT_FMT_NL_DEFAULT)) > return 0; > return oalog2_mul(oa, PT_GRANULE_LG2SZ); > diff --git a/drivers/iommu/generic_pt/fmt/x86_64.h b/drivers/iommu/generic_pt/fmt/x86_64.h > index be2a0a770f903f..d33b2fcd865b84 100644 > --- a/drivers/iommu/generic_pt/fmt/x86_64.h > +++ b/drivers/iommu/generic_pt/fmt/x86_64.h > @@ -79,14 +79,22 @@ enum { > > static inline pt_oaddr_t x86_64_pt_table_pa(const struct pt_state *pts) > { > - return oalog2_mul(FIELD_GET(X86_64_FMT_OA, pts->entry), > + u64 entry = pts->entry; > + > + if (pts_feature(pts, PT_FEAT_X86_64_AMD_ENCRYPT_TABLES)) > + entry = __sme_clr(entry); > + return oalog2_mul(FIELD_GET(X86_64_FMT_OA, entry), > PT_TABLEMEM_LG2SZ); > } > #define pt_table_pa x86_64_pt_table_pa > > static inline pt_oaddr_t x86_64_pt_entry_oa(const struct pt_state *pts) > { > - return oalog2_mul(FIELD_GET(X86_64_FMT_OA, pts->entry), > + u64 entry = pts->entry; > + > + if (pts_feature(pts, PT_FEAT_X86_64_AMD_ENCRYPT_TABLES)) > + entry = __sme_clr(entry); > + return oalog2_mul(FIELD_GET(X86_64_FMT_OA, entry), > PT_GRANULE_LG2SZ); > } > #define pt_entry_oa x86_64_pt_entry_oa