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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>
Cc: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com,
	 tony.luck@intel.com, babu.moger@amd.com, fenghuay@nvidia.com,
	 peternewman@google.com, zide.chen@intel.com,
	dapeng1.mi@linux.intel.com,  ben.horgan@arm.com,
	yu.c.chen@intel.com, jason.zeng@intel.com,
	 linux-kselftest@vger.kernel.org,
	LKML <linux-kernel@vger.kernel.org>,
	 patches@lists.linux.dev
Subject: Re: [PATCH v3 08/10] selftests/resctrl: Remove requirement on cache miss rate
Date: Tue, 31 Mar 2026 11:07:16 +0300 (EEST)	[thread overview]
Message-ID: <42de2e76-5962-caf5-3b8d-453784b43af2@linux.intel.com> (raw)
In-Reply-To: <ef8bb064-f562-4237-ac72-fc2c00a5708e@intel.com>

[-- Attachment #1: Type: text/plain, Size: 3687 bytes --]

On Fri, 27 Mar 2026, Reinette Chatre wrote:

> Hi Ilpo,
> 
> On 3/27/26 10:45 AM, Ilpo Järvinen wrote:
> > On Fri, 13 Mar 2026, Reinette Chatre wrote:
> >> -/*
> >> - * Minimum difference in LLC misses between a test with n+1 bits CBM to the
> >> - * test with n bits is MIN_DIFF_PERCENT_PER_BIT * (n - 1). With e.g. 5 vs 4
> >> - * bits in the CBM mask, the minimum difference must be at least
> >> - * MIN_DIFF_PERCENT_PER_BIT * (4 - 1) = 3 percent.
> >> - *
> >> - * The relationship between number of used CBM bits and difference in LLC
> >> - * misses is not expected to be linear. With a small number of bits, the
> >> - * margin is smaller than with larger number of bits. For selftest purposes,
> >> - * however, linear approach is enough because ultimately only pass/fail
> >> - * decision has to be made and distinction between strong and stronger
> >> - * signal is irrelevant.
> >> - */
> >> -#define MIN_DIFF_PERCENT_PER_BIT	1UL
> >> -
> >>  static int show_results_info(__u64 sum_llc_val, int no_of_bits,
> >>  			     unsigned long cache_span,
> >> -			     unsigned long min_diff_percent,
> >>  			     unsigned long num_of_runs, bool platform,
> >>  			     __s64 *prev_avg_llc_val)
> >>  {
> >>  	__u64 avg_llc_val = 0;
> >> -	float avg_diff;
> >>  	int ret = 0;
> >>  
> >>  	avg_llc_val = sum_llc_val / num_of_runs;
> >>  	if (*prev_avg_llc_val) {
> >> -		float delta = (__s64)(avg_llc_val - *prev_avg_llc_val);
> >> -
> >> -		avg_diff = delta / *prev_avg_llc_val;
> >> -		ret = platform && (avg_diff * 100) < (float)min_diff_percent;
> >> -
> >> -		ksft_print_msg("%s Check cache miss rate changed more than %.1f%%\n",
> >> -			       ret ? "Fail:" : "Pass:", (float)min_diff_percent);
> >> +		ret = platform && (avg_llc_val < *prev_avg_llc_val);
> >>  
> >> -		ksft_print_msg("Percent diff=%.1f\n", avg_diff * 100);
> >> +		ksft_print_msg("%s Check cache miss rate increased\n",
> >> +			       ret ? "Fail:" : "Pass:");
> > 
> > While I'm fine with removing the amount of change check, this no longer 
> > shows any numbers which would be a bit annoying if/when there's a failure.
> > 
> 
> This snippet only removes display of the number that is no longer computed ("avg_diff").
> The values that are compared now, avg_llc_val and it previous value, are printed
> in the call to show_cache_info() that follows this snippet but is not visible in the diff.
>  
> Below is an example of what a user running the CAT test will see after these changes.
> Since show_cache_info() always prints avg_llc_val the user can obtain insight into failure
> by considering it and its previous measurement.
> 
> # Starting L3_CAT test ...
> # Mounting resctrl to "/sys/fs/resctrl"
> # Cache size :117964800
> # Writing benchmark parameters to resctrl FS
> # Write schema "L2:1=0x1" to resctrl FS
> # Write schema "L3:0=1fc0" to resctrl FS
> # Write schema "L3:0=3f" to resctrl FS
> # Write schema "L3:0=1ff0" to resctrl FS
> # Write schema "L3:0=f" to resctrl FS
> # Write schema "L3:0=1ffc" to resctrl FS
> # Write schema "L3:0=3" to resctrl FS
> # Checking for pass/fail
> # Number of bits: 6
> # Average LLC val: 445092
> # Cache span (lines): 737280
> # Pass: Check cache miss rate increased
> # Number of bits: 4
> # Average LLC val: 724472
> # Cache span (lines): 491520
> # Pass: Check cache miss rate increased
> # Number of bits: 2
> # Average LLC val: 1085470
> # Cache span (lines): 245760
> ok 4 L3_CAT: test

Okay, I didn't remember there was another place printing the numbers.
No problem with this then,

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

-- 
 i.

  reply	other threads:[~2026-03-31  8:07 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-13 20:32 [PATCH v3 00/10] selftests/resctrl: Fixes and improvements focused on Intel platforms Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 01/10] selftests/resctrl: Improve accuracy of cache occupancy test Reinette Chatre
2026-03-26 12:44   ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 02/10] selftests/resctrl: Reduce interference from L2 occupancy during " Reinette Chatre
2026-03-26 12:56   ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 03/10] selftests/resctrl: Do not store iMC counter value in counter config structure Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 04/10] selftests/resctrl: Prepare for parsing multiple events per iMC Reinette Chatre
2026-03-26 13:03   ` Ilpo Järvinen
2026-03-26 14:34     ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 05/10] selftests/resctrl: Support multiple events associated with iMC Reinette Chatre
2026-03-27 17:28   ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 06/10] selftests/resctrl: Increase size of buffer used in MBM and MBA tests Reinette Chatre
2026-03-27 17:30   ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 07/10] selftests/resctrl: Raise threshold at which MBM and PMU values are compared Reinette Chatre
2026-03-27 17:34   ` Ilpo Järvinen
2026-03-27 23:19     ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 08/10] selftests/resctrl: Remove requirement on cache miss rate Reinette Chatre
2026-03-27 17:45   ` Ilpo Järvinen
2026-03-27 23:21     ` Reinette Chatre
2026-03-31  8:07       ` Ilpo Järvinen [this message]
2026-03-31 17:39         ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 09/10] selftests/resctrl: Simplify perf usage in CAT test Reinette Chatre
2026-03-27 17:47   ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 10/10] selftests/resctrl: Reduce L2 impact on " Reinette Chatre
2026-03-27 17:49   ` Ilpo Järvinen
2026-03-27 23:22     ` Reinette Chatre
2026-03-31 19:13 ` [PATCH v3 00/10] selftests/resctrl: Fixes and improvements focused on Intel platforms Shuah Khan
2026-03-31 20:22   ` Reinette Chatre

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