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Fri, 25 Apr 2025 22:59:22 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 17/22] iommu/arm-smmu-v3-iommufd: Support implementation-defined hw_info Date: Fri, 25 Apr 2025 22:58:12 -0700 Message-ID: <56f048cdc9cd8bf1569434633d709d07a78e9430.1745646960.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001505:EE_|CYYPR12MB8853:EE_ X-MS-Office365-Filtering-Correlation-Id: f3eca068-21e1-4f69-fbfc-08dd8487836c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?t/Y6bmeQvwe2pO6PKlxDbk67JdzLCC62dfjn4R5OiXp475sE4mbpKGbySyW1?= =?us-ascii?Q?EU0b3zgs2/aNmS8yWV/dokqs2yu6fUdPg9jb1EuKE+nDqK8Oc4+D3t14Fu3N?= =?us-ascii?Q?jg9HpU9VKruK7eriiOr8myH9UE/3+JrUP581TM8XbhQV3bzPBLHyD5w8mWdr?= =?us-ascii?Q?oA8eSMDFtzYNAwGkgpfKLvVeH1W4JHKq2D3jBDdGquuSVcJjfxtSVj3Sk5P3?= =?us-ascii?Q?4UME7ZCGnEAUyaofIot6hQWFswurHUUtzb6/RE0EwcF7NkvGy/HjsXFL7toi?= =?us-ascii?Q?TTsmbWUPKzUSFrmV2wPexKqiF0KQQE0q9Ibf3WV+YeirHKf6Xer/8izi+q6h?= =?us-ascii?Q?7buDsgz703rWtW0SJtVX1w/ssiWDnnqEgTgO+2EeElcFOP8mowoDK86zZwWP?= =?us-ascii?Q?cvcDnx8FZtaLACPSnA2VPIU0kckiDmusdujLa4x64kW0/jWaKPB+Ur/CW0ln?= =?us-ascii?Q?GyKeA/3KK8IPeReYHR9BHGcWDNImv2hzCKQu5HqsVg4BuG1g5bR5pE4rdZnz?= =?us-ascii?Q?PDyObrqPUbWJGKH5rT3EgYgPa+gWFnKEZtDR973I6dprZD5uTip1ZuencAkS?= =?us-ascii?Q?SNDZn46krpmioVJGNHs4aCtT/b7sDllJcRqQ4Zb1p1UrWmpfLiGE7ww5m+k5?= =?us-ascii?Q?ijO9oDgs1ddrSu9QjjrQBqTsuiZkEZAH2ZVY6o1zE4pe2SmjxqHh5itjisV0?= =?us-ascii?Q?6l3VeoOTRB2wgmlfcJRjKy/v63GYpk8eBJLJRoGobbGE5/qGpA70nucVGdv7?= =?us-ascii?Q?h7USO4LlUbDEsE8m09iPa4zR4fKi+AZ+rAaJ+Es7DmBBET0I4oFX4staUQtY?= =?us-ascii?Q?Qc+2m01KICCs37BunewyIg9KNH3KC9CJZr2JCGrNjs/SshsfbfUphRy0MERG?= =?us-ascii?Q?LoCO9fTV1u5+RLRcpcG1X0mTCtoxB8BY9vmppGN0PXgsksavPSKMcYaaoQ9f?= =?us-ascii?Q?9Ybaq0ZhwrBsdRgYrnxSMqEtew3R6nee2t1C0v6fxI6V8P1finDCm0lf2RKt?= =?us-ascii?Q?eGtHk/i/Rf9eioVC+a6ltK7YqRM2BmgAR4Ijh7yvth0j7UPX2S4O1HezR5ZK?= =?us-ascii?Q?fT7sn86QJxo1nPVfw2QkzBkfpjGsXwHpOodHLi5FdOtgilevODjZuhaYM4pR?= =?us-ascii?Q?yV6834wSroIu4bUVEzWg/BWIMa2kp4A85QpWAxrCo+VH3VkQAs13lTc9zj26?= =?us-ascii?Q?3MDcoFcaUF8B8OR+5cyzpOR+MTxBAUmHPuoBW8h0nozpdWm4FHzZC8Sjr64m?= =?us-ascii?Q?Q7V9G2yDYOZOK0yZW3vVjLS3bCJgf/4d+BeJTBhZ/Nt0RoTgJJHOX/fD7ji5?= =?us-ascii?Q?9WUb+PI0GmWA1LDmGgc2cFPpaHBHdGKhTXm2ykAJppo9DbmbdKq7H9Sx+4YI?= =?us-ascii?Q?FZqHTwYfWyX8Wl27HwMutt669hUj4D/eo/5bpyf5tCJo6DUY4FqrM/di7FTU?= =?us-ascii?Q?xXZQK2CHj0luvdy+++vy/sWfKmE4KggfWhbDawcvkWrZjv6612coFZhZpJL2?= =?us-ascii?Q?hSUecSuueScJqBIFD1zxUoCKMmjPYuvxgELS?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2025 05:59:31.5481 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3eca068-21e1-4f69-fbfc-08dd8487836c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001505.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8853 Repurpose the @__reserved field in the struct iommu_hw_info_arm_smmuv3, to an HW implementation-defined field @impl. This will be used by Tegra241 CMDQV implementation on top of a standard ARM SMMUv3 IOMMU. The @impl will be only valid if @flags is set with an implementation-defined flag. Thus in the driver-level, add an hw_info impl op that will return such a flag to use the impl field. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + include/uapi/linux/iommufd.h | 4 ++-- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 16 +++++++++++++--- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index a5835af72417..bab7a9ce1283 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -726,6 +726,7 @@ struct arm_smmu_impl_ops { struct arm_smmu_domain *smmu_domain, struct iommufd_ctx *ictx, unsigned int viommu_type, const struct iommu_user_data *user_data); + u32 (*hw_info)(struct arm_smmu_device *smmu, u32 *impl); }; /* An SMMUv3 instance */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 06a763fda47f..b2614f0f1547 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -554,7 +554,7 @@ struct iommu_hw_info_vtd { * (IOMMU_HW_INFO_TYPE_ARM_SMMUV3) * * @flags: Must be set to 0 - * @__reserved: Must be 0 + * @impl: Must be 0 * @idr: Implemented features for ARM SMMU Non-secure programming interface * @iidr: Information about the implementation and implementer of ARM SMMU, * and architecture version supported @@ -585,7 +585,7 @@ struct iommu_hw_info_vtd { */ struct iommu_hw_info_arm_smmuv3 { __u32 flags; - __u32 __reserved; + __u32 impl; __u32 idr[6]; __u32 iidr; __u32 aidr; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index a8a78131702d..63861c60b615 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -10,7 +10,9 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type) { struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_device *smmu = master->smmu; struct iommu_hw_info_arm_smmuv3 *info; + u32 flags = 0, impl = 0; u32 __iomem *base_idr; unsigned int i; @@ -18,15 +20,23 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type) if (!info) return ERR_PTR(-ENOMEM); - base_idr = master->smmu->base + ARM_SMMU_IDR0; + base_idr = smmu->base + ARM_SMMU_IDR0; for (i = 0; i <= 5; i++) info->idr[i] = readl_relaxed(base_idr + i); - info->iidr = readl_relaxed(master->smmu->base + ARM_SMMU_IIDR); - info->aidr = readl_relaxed(master->smmu->base + ARM_SMMU_AIDR); + info->iidr = readl_relaxed(smmu->base + ARM_SMMU_IIDR); + info->aidr = readl_relaxed(smmu->base + ARM_SMMU_AIDR); *length = sizeof(*info); *type = IOMMU_HW_INFO_TYPE_ARM_SMMUV3; + if (smmu->impl_ops && smmu->impl_ops->hw_info) { + flags = smmu->impl_ops->hw_info(smmu, &impl); + if (flags) { + info->impl = impl; + info->flags |= flags; + } + } + return info; } -- 2.43.0