Re: [PATCH v2 04/10] iommupt: Flush the CPU cache after any writes to the page table

[Baolu Lu <baolu.lu@linux.intel.com>]

On 9/22/25 22:42, Jason Gunthorpe wrote:
> On Mon, Sep 22, 2025 at 10:12:15AM +0800, Baolu Lu wrote:
>> On 8/27/25 01:26, Jason Gunthorpe wrote:
>>> @@ -195,6 +218,10 @@ static void record_dirty(struct pt_state *pts,
>>>    				dirty_len);
>>>    	if (!(dirty->flags & IOMMU_DIRTY_NO_CLEAR)) {
>>> +		/*
>>> +		 * No write log required because DMA incoherence and atomic
>>> +		 * dirty tracking bits can't work together
>>> +		 */
>>
>> Could you elaborate a bit on this comment? Is this a hardware or
>> software requirement?
> 
> dirty tracking relies on some kind of atomic operation coherent
> between the IOMMU and CPU. AFAIK this is not possible on any arch
> unless the IOMMU is working coherently.

Yes, fair enough.

> 
>> Are there any software checks or enforcement in
>> the subsystem?
> 
> I expect the iommu drivers to exclude this combination.

For VT-d driver, perhaps we could add below check:

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index dff2d895b8ab..563ded2eb3b3 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -3370,7 +3370,7 @@ intel_iommu_domain_alloc_second_stage(struct 
device *dev,
         if (((flags & IOMMU_HWPT_ALLOC_NEST_PARENT) &&
              !nested_supported(iommu)) ||
             ((flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING) &&
-            !ssads_supported(iommu)))
+            (!ssads_supported(iommu) || !ecap_smpwc(iommu->ecap))))
                 return ERR_PTR(-EOPNOTSUPP);

         /* Legacy mode always supports second stage */

Thanks,
baolu