From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E6981F5E9 for ; Mon, 18 Sep 2023 16:58:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695056299; x=1726592299; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=ziHw/sy984NIKoppaIYXIKlbyWVZyfzywUzaodCwEt4=; b=IwW60tA6ccmRYbumrF8fifrQSla0PyJ69esOeIwztAU4c5fFt8sdODN9 cMvbrLGFotAx6O0B55rotjE2M9oMfBiljf9e5p2btGUfa5IOavci6UGcL ToifvYkAukjDsrjy4LdCIli/ykEorsK94hsJUx0Chv0meG57Y/FtUIgc3 LQMKDeR/Dqw35EMofMpw3BwfGXhYy+Wy01Lp8JH4oijkarNXLfZSuOFYm o8QBLL22zXYYB9hD+PXoZapwfg96HVSE8in5d1qwnOSnUWUE9rQPaAyAH 6FDgIY0c/8DW6CVH0OiVqdYGVfokV82WyRAz0YjOAFwuE5m7IJIASYXZE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10837"; a="383537648" X-IronPort-AV: E=Sophos;i="6.02,157,1688454000"; d="scan'208";a="383537648" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2023 09:58:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10837"; a="992799245" X-IronPort-AV: E=Sophos;i="6.02,157,1688454000"; d="scan'208";a="992799245" Received: from ecochran-mobl1.amr.corp.intel.com (HELO [10.212.244.237]) ([10.212.244.237]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2023 09:58:03 -0700 Message-ID: <789bc8e6-882a-3dfb-7381-fd9b5aca3c77@intel.com> Date: Mon, 18 Sep 2023 09:58:02 -0700 Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 03/10] platform/x86/intel/ifs: Image loading for new generations Content-Language: en-US To: "Joseph, Jithu" , =?UTF-8?Q?Ilpo_J=c3=a4rvinen?= , "Luck, Tony" Cc: Hans de Goede , "markgross@kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "rostedt@goodmis.org" , "Raj, Ashok" , LKML , "platform-driver-x86@vger.kernel.org" , "patches@lists.linux.dev" , "Shankar, Ravi V" , "Xu, Pengfei" References: <20230913183348.1349409-1-jithu.joseph@intel.com> <20230913183348.1349409-4-jithu.joseph@intel.com> <10fe57c-c926-9de4-be84-21a0f8abab6d@linux.intel.com> <56b486ce-2a6e-c4c7-8bc5-ceeb7119ba1@linux.intel.com> <826a2b32-bd6a-900a-19fa-e169fcf0d29d@intel.com> From: Dave Hansen In-Reply-To: <826a2b32-bd6a-900a-19fa-e169fcf0d29d@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 9/18/23 09:51, Joseph, Jithu wrote: > > On 9/18/2023 9:29 AM, Ilpo Järvinen wrote: > >> In this case it is not just about the bitfield itself nor the bit >> allocation order but sharing the storage unit with another member, and to >> further complicate things, members have different alignment requirement >> too (32-bit aligned u8 followed by u32 bitfield). >> > I too verified that the size of the whole structure matches that of MSR 64 bits (8 bytes). > > Initially when IFS scan was added the all MSR structure members were bit-fields, later there was a suggestion to > use basic C types if applicable during subsequent Array BIST patch series. I followed this approach with the current patch series . > > I will change the current series to use all bit-field MSR structures in v2, given mixing basic types and bitfields is a a source of confusion That's the wrong direction. :) What is more obviously correct. This: struct { u16 valid_chunks; u16 total_chunks; u8 error_code; u8 rsvd1; u8 rsvd2; u8 rsvd3; }; or this: struct { u16 valid_chunks; u16 total_chunks; u8 error_code; u32 error_code :8; u32 rsvd :24; }; ?