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[34.140.232.180]) by smtp.gmail.com with ESMTPSA id q20-20020a05600c46d400b004147db8a91asm9518815wmo.40.2024.03.25.14.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Mar 2024 14:06:27 -0700 (PDT) Date: Mon, 25 Mar 2024 21:06:23 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameerali Kolothum Thodi Subject: Re: [PATCH v5 00/27] Update SMMUv3 to the modern iommu API (part 2/3) Message-ID: References: <0-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com> <20240325143503.GF110546@nvidia.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240325143503.GF110546@nvidia.com> On Mon, Mar 25, 2024 at 11:35:03AM -0300, Jason Gunthorpe wrote: > On Sat, Mar 23, 2024 at 01:38:04PM +0000, Mostafa Saleh wrote: > > Hi Jason, > > > > On Mon, Mar 04, 2024 at 07:43:48PM -0400, Jason Gunthorpe wrote: > > > Continuing the work of part 1 this focuses on the CD, PASID and SVA > > > components: > > > > > > - attach_dev failure does not change the HW configuration. > > > > > > - Full PASID API support including: > > > - S1/SVA domains attached to PASIDs > > > > I am still going through the series, but I see at the end the main SMMUv3 > > driver has set_dev_pasid operation, are there any in-tree drivers that > > use that? (and how can I test it). > > Not yet, but some will be coming. Currently only Intel driver supports > it, but Intel HW has other problems making it unusable.. > > A big part of the effort here is to enable the platform ecosystem so > devices and drivers can use it. Moritz has access to a device that > can exercise this, though we are still working on it. > Just out of curiosity, are there plans to upstream that driver? > > > - IDENTITY/BLOCKED/S1 attached to RID > > > - Change of the RID domain while PASIDs are attached > > > > > > - Streamlined SVA support using the core infrastructure > > > > > > - Hitless, whenever possible, change between two domains > > > > Can you please clarify what cases are expected to be hitless? > > From what I see if ASID and TTB0 changes that would break the CD. > > Right. For CD it is only the SVA mm release flow, setting EPD0. > I see, thanks for confirming, I am still going through the series, but I now wonder if this case is worth the extra complexity, unlike the STE where the hitless transition was usefull in many cases. Thanks, Mostafa.