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Mon, 13 May 2024 14:23:20 -0700 Date: Mon, 13 May 2024 14:23:18 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , Joerg Roedel , , Robin Murphy , Will Deacon , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , , Shameerali Kolothum Thodi Subject: Re: [PATCH v7 10/14] iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain Message-ID: References: <0-v7-9597c885796c+d2-smmuv3_newapi_p2b_jgg@nvidia.com> <10-v7-9597c885796c+d2-smmuv3_newapi_p2b_jgg@nvidia.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <10-v7-9597c885796c+d2-smmuv3_newapi_p2b_jgg@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB51:EE_|IA1PR12MB6187:EE_ X-MS-Office365-Filtering-Correlation-Id: d51d7fc1-7127-4ddb-d693-08dc7392f6c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|82310400017|7416005|1800799015; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2024 21:23:42.0422 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d51d7fc1-7127-4ddb-d693-08dc7392f6c9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB51.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6187 On Wed, May 08, 2024 at 03:57:18PM -0300, Jason Gunthorpe wrote: > This removes all the notifier de-duplication logic in the driver and > relies on the core code to de-duplicate and allocate only one SVA domain > per mm per smmu instance. This naturally gives a 1:1 relationship between > SVA domain and mmu notifier. > > It is a significant simplication of the flow, as we end up with a single > struct arm_smmu_domain for each MM and the invalidation can then be > shifted to properly use the masters list like S1/S2 do. > > Remove all of the previous mmu_notifier, bond, shared cd, and cd refcount > logic entirely. > > The logic here is tightly wound together with the unusued BTM > support. Since the BTM logic requires holding all the iommu_domains in a > global ASID xarray it conflicts with the design to have a single SVA > domain per PASID, as multiple SMMU instances will need to have different > domains. > > Following patches resolve this by making the ASID xarray per-instance > instead of global. However, converting the BTM code over to this > methodology requires many changes. > > Thus, since ARM_SMMU_FEAT_BTM is never enabled, remove the parts of the > BTM support for ASID sharing that interact with SVA as well. > > A followup series is already working on fully enabling the BTM support, > that requires iommufd's VIOMMU feature to bring in the KVM's VMID as > well. It will come with an already written patch to bring back the ASID > sharing using a per-instance ASID xarray. > > https://lore.kernel.org/linux-iommu/20240208151837.35068-1-shameerali.kolothum.thodi@huawei.com/ > https://lore.kernel.org/linux-iommu/26-v6-228e7adf25eb+4155-smmuv3_newapi_p2_jgg@nvidia.com/ > > Tested-by: Nicolin Chen > Tested-by: Shameer Kolothum > Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen > static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) > { > - kfree(mn_to_smmu(mn)); > + struct arm_smmu_domain *smmu_domain = > + container_of(mn, struct arm_smmu_domain, mmu_notifier); > + > + kfree(smmu_domain); Would it be cleaner to refactor mn_to_smmu to mn_to_smmu_domain? Otherwise, would it feel simpler by just kfree(container_of(mn, struct arm_smmu_domain, mmu_notifier)); Thanks Nicolin