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Tue, 4 Jun 2024 12:28:13 -0700 Date: Tue, 4 Jun 2024 12:28:11 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , Joerg Roedel , , Robin Murphy , Will Deacon , Michael Shavit , , Ryan Roberts , Mostafa Saleh Subject: Re: [PATCH 1/7] iommu/arm-smmu-v3: Split struct arm_smmu_strtab_cfg.strtab Message-ID: References: <0-v1-1b720dce51d1+4f44-smmuv3_tidy_jgg@nvidia.com> <1-v1-1b720dce51d1+4f44-smmuv3_tidy_jgg@nvidia.com> <20240604125955.GH19897@nvidia.com> <20240604190247.GP19897@nvidia.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240604190247.GP19897@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|SA3PR12MB8802:EE_ X-MS-Office365-Filtering-Correlation-Id: 9105699d-39cb-4733-84da-08dc84cc8451 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|376005|1800799015|36860700004; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2024 19:28:30.6178 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9105699d-39cb-4733-84da-08dc84cc8451 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8802 On Tue, Jun 04, 2024 at 04:02:47PM -0300, Jason Gunthorpe wrote: > On Tue, Jun 04, 2024 at 11:28:05AM -0700, Nicolin Chen wrote: > > On Tue, Jun 04, 2024 at 09:59:55AM -0300, Jason Gunthorpe wrote: > > > On Tue, Jun 04, 2024 at 01:32:20AM -0700, Nicolin Chen wrote: > > > > On Mon, Jun 03, 2024 at 07:31:27PM -0300, Jason Gunthorpe wrote: > > > > The "struct arm_smmu_strtab_l1_desc" seems to be only used at one > > > > place in arm_smmu_init_l2_strtab(). So, how about: > > > > > > I didn't do it but, it would make some of the maths more obvious > > > if we encoded the table structure in the types: > > > > > > struct arm_smmu_strtab_l2_stes { > > > struct arm_smmu_ste l2[256]; > > > }; > > > > I personally prefer this one, though why 256? > > #define STRTAB_SPLIT 8 Oh right! And similarly, "struct arm_smmu_cd l2[1024]". > > struct arm_smmu_strtab_linear { > > struct arm_smmu_ste *ste; > > dma_addr_t ste_dma; > > }; > > struct arm_smmu_strtab_l1 { > > struct arm_smmu_strtab_l1_desc *l1; > > num_l1_ents too Yea, missed that. > > struct arm_smmu_device { > > ... > > union { > > struct arm_smmu_strtab_linear linear; > > struct arm_smmu_strtab_l1 l1; > > } strtab; > > ... > > }; > > Yes! That is quite readable and understandable! I was relucant to do > much more than just the small change Will asked about, and even that > expanded.. Let me see if I can reasonably squeeze that into a small > number of patches. Yea, I hesitated too at the beginning, until I saw Mostafa suggest something further. > > Only arm_smmu_device_reset() really needs strtab_base/_cfg values > > that we could compute them over there, given that there are quite > > amount of smmu->features checking already? > > Certainly could do, but that seems to have less advantage.. Well, either way sounds good to me. I was just considering that we already did something similar with s1/s2/cd cfg values. Yet, not a problem to continue storing these two. Thanks Nicolin