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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>
Cc: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com,
	 tony.luck@intel.com, babu.moger@amd.com, fenghuay@nvidia.com,
	 peternewman@google.com, zide.chen@intel.com,
	dapeng1.mi@linux.intel.com,  ben.horgan@arm.com,
	yu.c.chen@intel.com, linux-kselftest@vger.kernel.org,
	 LKML <linux-kernel@vger.kernel.org>,
	patches@lists.linux.dev
Subject: Re: [PATCH v2 9/9] selftests/resctrl: Reduce L2 impact on CAT test
Date: Fri, 6 Mar 2026 12:35:04 +0200 (EET)	[thread overview]
Message-ID: <a36e9760-f59d-5bfe-640f-7ec8679336d4@linux.intel.com> (raw)
In-Reply-To: <74657e85c607b1494c898353087fa40e80a8af01.1772582958.git.reinette.chatre@intel.com>

On Tue, 3 Mar 2026, Reinette Chatre wrote:

> The L3 CAT test loads a buffer into cache that is proportional to the L3
> size allocated for the workload and measures cache misses when accessing
> the buffer as a test of L3 occupancy. When loading the buffer it can be
> assumed that a portion of the buffer will be loaded into the L2 cache and
> depending on cache design may not be present in L3. It is thus possible
> for data to not be in L3 but also not trigger an L3 cache miss when
> accessed.
> 
> Reduce impact of L2 on the L3 CAT test by, if L2 allocation is supported,
> minimizing the portion of L2 that the workload can allocate into. This
> encourages most of buffer to be loaded into L3 and support better
> comparison between buffer size, cache portion, and cache misses when
> accessing the buffer.
> 
> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
> ---
>  tools/testing/selftests/resctrl/cat_test.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
> index 6aac03147d41..26062684a9f4 100644
> --- a/tools/testing/selftests/resctrl/cat_test.c
> +++ b/tools/testing/selftests/resctrl/cat_test.c
> @@ -157,6 +157,12 @@ static int cat_test(const struct resctrl_test *test,
>  	if (ret)
>  		goto reset_affinity;
>  
> +	if (!strcmp(test->resource, "L3") && resctrl_resource_exists("L2")) {
> +		ret = write_schemata(param->ctrlgrp, "0x1", uparams->cpu, "L2");
> +		if (ret)
> +			goto reset_affinity;
> +	}

This looks similar to what you did in the CMT test. Maybe add a common 
function for minimizing L2 cache size so it doesn't have to duplicated to 
all L3 related tests.

> +
>  	perf_event_attr_initialize(&pea, PERF_COUNT_HW_CACHE_MISSES);
>  	pe_fd = perf_open(&pea, bm_pid, uparams->cpu);
>  	if (pe_fd < 0) {
> 

-- 
 i.


  reply	other threads:[~2026-03-06 10:35 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-04  0:19 [PATCH v2 0/9] selftests/resctrl: Fixes and improvements focused on Intel platforms Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 1/9] selftests/resctrl: Improve accuracy of cache occupancy test Reinette Chatre
2026-03-06  9:47   ` Ilpo Järvinen
2026-03-06 19:24     ` Reinette Chatre
2026-03-09  7:44       ` Ilpo Järvinen
2026-03-04  0:19 ` [PATCH v2 2/9] selftests/resctrl: Do not store iMC counter value in counter config structure Reinette Chatre
2026-03-06  9:51   ` Ilpo Järvinen
2026-03-06 19:25     ` Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 3/9] selftests/resctrl: Prepare for parsing multiple events per iMC Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 4/9] selftests/resctrl: Support multiple events associated with iMC Reinette Chatre
2026-03-06 10:18   ` Ilpo Järvinen
2026-03-06 19:25     ` Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 5/9] selftests/resctrl: Increase size of buffer used in MBM and MBA tests Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 6/9] selftests/resctrl: Raise threshold at which MBM and PMU values are compared Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 7/9] selftests/resctrl: Remove requirement on cache miss rate Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 8/9] selftests/resctrl: Simplify perf usage in CAT test Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 9/9] selftests/resctrl: Reduce L2 impact on " Reinette Chatre
2026-03-06 10:35   ` Ilpo Järvinen [this message]
2026-03-06 19:26     ` Reinette Chatre
2026-03-04 15:18 ` [PATCH v2 0/9] selftests/resctrl: Fixes and improvements focused on Intel platforms Chen, Yu C

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