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Thu, 15 May 2025 21:10:26 -0700 Date: Thu, 15 May 2025 21:10:25 -0700 From: Nicolin Chen To: "Tian, Kevin" CC: "jgg@nvidia.com" , "corbet@lwn.net" , "will@kernel.org" , "bagasdotme@gmail.com" , "robin.murphy@arm.com" , "joro@8bytes.org" , "thierry.reding@gmail.com" , "vdumpa@nvidia.com" , "jonathanh@nvidia.com" , "shuah@kernel.org" , "jsnitsel@redhat.com" , "nathan@kernel.org" , "peterz@infradead.org" , "Liu, Yi L" , "mshavit@google.com" , "praan@google.com" , "zhangzekun11@huawei.com" , "iommu@lists.linux.dev" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "patches@lists.linux.dev" , "mochs@nvidia.com" , "alok.a.tiwari@oracle.com" , "vasant.hegde@amd.com" Subject: Re: [PATCH v4 22/23] iommu/tegra241-cmdqv: Add user-space use support Message-ID: References: Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2025 04:10:40.6261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c74ce62-1967-4017-e60e-08dd942f9ef3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4327 On Fri, May 16, 2025 at 04:00:58AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen > > Sent: Friday, May 16, 2025 1:14 AM > > > > On Thu, May 15, 2025 at 08:27:17AM +0000, Tian, Kevin wrote: > > > > From: Nicolin Chen > > > > Sent: Friday, May 9, 2025 11:03 AM > > > > > > > > /** > > > > * struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware > > > > information > > > > * (IOMMU_HW_INFO_TYPE_ARM_SMMUV3) > > > > * > > > > - * @flags: Must be set to 0 > > > > - * @impl: Must be 0 > > > > + * @flags: Combination of enum iommu_hw_info_arm_smmuv3_flags > > > > + * @impl: Implementation-defined bits when the following flags are set: > > > > + * - IOMMU_HW_INFO_ARM_SMMUV3_HAS_TEGRA241_CMDQV > > > > + * Bits[15:12] - Log2 of the total number of SID replacements > > > > + * Bits[11:08] - Log2 of the total number of VINTFs per vIOMMU > > > > + * Bits[07:04] - Log2 of the total number of VCMDQs per vIOMMU > > > > + * Bits[03:00] - Version number for the CMDQ-V HW > > > > > > hmm throughout this series I drew an equation between VINTF > > > and vIOMMU. Not sure how multiple VINTFs can be represented > > > w/o introducing more objects. Do we want to keep such info here? > > > > You are right that VINTF=vIOMMU. This is a per SMMU instance ioctl. > > So, each VM should only have one VTINF/vIOMMU per SMMU instance. > > > > For multi-VINTF (multi-vIOMMU) case, there needs to be more SMMUs > > backing passthrough devices being assigned to the VM. > > > > What exactly the concern of keeping this info here? > > First, you agreed that VINTF=vIOMMU, then "total number of VINTFs > per vIOMMU" doesn't make sense as it's fixed to 1 in concept. > > Then, each VM can only get one VINTF/vIOMMU per SMMU instance, > and this ioctl is per SMMU instance. This also implies that only one > VINTF can be reported in the ioctl. > > In multi-VINTF case, the VM should get 1VINTF per ioctl from each > SMMU backing passthrough devices. > > Then what is the point of " Bits[11:08] - Log2 of the total number > of VINTFs per vIOMMU "? It was not there in the previous version. Pranjal pointed out that it was missing a field. You are right that this field must set to 0, indicating only single VINTF is allowed. Given Jason's comments about this impl rework (to a data structure), I think I will just drop this number of VTINFs. Instead will add a line of comments say that VMM should set this field to 0, i.e. only provide VM one VINTF per SMMU. Thanks Nicolin