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Fri, 13 Jun 2025 14:10:18 -0700 Date: Fri, 13 Jun 2025 14:10:15 -0700 From: Nicolin Chen To: Bjorn Helgaas CC: Jason Gunthorpe , Robin Murphy , , , , , , , , , Subject: Re: [PATCH RFC v1 0/2] iommu&pci: Disable ATS during FLR resets Message-ID: References: <20250610163045.GI543171@nvidia.com> <20250613192709.GA971579@bhelgaas> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250613192709.GA971579@bhelgaas> X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD74:EE_|DM4PR12MB8559:EE_ X-MS-Office365-Filtering-Correlation-Id: 9c17888c-95fa-4e69-6711-08ddaabebe67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?vdiPoIVsC+0Ne8MMd4hNM8iYBZETO8lI3Bnj//39pAD8HHEvogv9WGZXWoel?= =?us-ascii?Q?mEObVWe0t3kfIfHnYzhf6lmPjIkqIaODr65UnvPf3M6LZ/GhZfRXAppVOPTi?= =?us-ascii?Q?D7pr/LoVXk8fv/3spWwkAlb/VQOoakhsUujQhL3PrbJi0QMok6A0ZIUf+9UI?= =?us-ascii?Q?JzHNwI3WE9coAOvyd/tvEQdJag2eVfB8J5x6RgWEBTQFSI/cvXJ4+ueZu64L?= =?us-ascii?Q?IlIj71U/ygNMnY6nMnoy85PucMzTmsT/CsRw9NLrO/xWO4qJTFCkzQjA7Bkd?= =?us-ascii?Q?HD2ztrel0ceLLr3xqCquNZg65AWkglFrFI3HkRufK2PcNuXEOhAJDUP43DTH?= =?us-ascii?Q?6rON4C8laJr7X6bdjw/pYCOSrgorF+d4+VNCTXECENKwK1E8ZkFK7dOCg4PU?= =?us-ascii?Q?c2c4ehFnXtaKRJrXEBMK/R6XPENiaccpYa4L43LQuQf8ejUpruwImanBUQMz?= =?us-ascii?Q?+y7VF8Sy6pIcT7PW+zlkw+b5sLFLuVSlX+B8Wy4Wk0HANCNm0+8g8AsTmRcm?= =?us-ascii?Q?9x5lWmnq3xFzx+7ANY9qcfdXYkyK/380Fz+WVvj7feWdFni/O94xjfTfZ9Zo?= =?us-ascii?Q?T7haY9pic8r+lwwJG9drv/68kc1Ur7uz8IQU9gTs07WKR4Q1P3iuLYRUOuEA?= =?us-ascii?Q?XK4YDIEsJ4h3CenHsuTjSJZj0gn5KKC7iDKmq8af7o6kTpIQFXheL9Jj/GI4?= =?us-ascii?Q?rvMuPfa3VOmV/IVcLRV6vwq78qkC3eeafQCjSbcBV32Rn9JMhKzPSDUsVw7a?= =?us-ascii?Q?725RQqgM8Ra4w/+gC/jFGNoOD/rftD/I190+FW1qV/+5383RwHCkVLguNMSi?= =?us-ascii?Q?Z6Z8U/I9AJnV+lhAB3FaACUWi7uDQcvhPPTXnWDl3w9NiQ1Viwe8u2IvydwI?= =?us-ascii?Q?shdQsLBPQjfckqMPLNE3kzgWN34me8aTJXIUhyfCVVxFoKtgg5RxVe0fYDwu?= =?us-ascii?Q?GcIkTI4PWUxQHmfJq0vs3rCGTZl07JtiGDP0dQ2u5/O+PSfF2T5BJOxP4fvq?= =?us-ascii?Q?Rd9H7B9/MNjFOEPBr9C2V0cA+M0YmolS41S0uUFMkWnzEnJSv+6WLBYnsyqZ?= =?us-ascii?Q?IRZJ+2UcZFJkz07zfMXa4/NUhUGGnA34V9hi9xsJ08qYM1AIgx1CnEF4+U/l?= =?us-ascii?Q?vmC6VEufOH7qhHTJ4UOdeAfnIyw2PDi6iELjVBeNTQK4tkO0UUAiMkpRtt+f?= =?us-ascii?Q?191igHt0bzqot3Tooe/c4erieuc2+iYy24OXsNrJsNSkjAdtsDXb93FtwAWm?= =?us-ascii?Q?jxd28uoiXAqiueKam87Aq/gxgPJVJBtkZV4PY4tevh1Y5lfkhVP0eM7/XUEL?= =?us-ascii?Q?vqS8T5eGHU0RO0D4kdCwXkWV4t8zJJKYFej+vJ/3uyFzu3IQe3fichIIg2Zd?= =?us-ascii?Q?2vVwZQfVsnSSZGz+mXHGUjsyacbbt9shq/nHCEU/JWMswEteP5DrLxZkIZyy?= =?us-ascii?Q?ungMf4PODuPfhlJk56L8F8NRKJihWI93SnfH2XknhNce4Z5sdpxPaGlXiaBN?= =?us-ascii?Q?o8vCSsXQ/c7ugNEAuu8gAiYlKPPFRF+/YsTK?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2025 21:10:36.9830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c17888c-95fa-4e69-6711-08ddaabebe67 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8559 On Fri, Jun 13, 2025 at 02:27:09PM -0500, Bjorn Helgaas wrote: > On Tue, Jun 10, 2025 at 01:30:45PM -0300, Jason Gunthorpe wrote: > > On Tue, Jun 10, 2025 at 04:37:58PM +0100, Robin Murphy wrote: > > > On 2025-06-09 7:45 pm, Nicolin Chen wrote: > > > > Hi all, > > > > > > > > Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software should disable ATS > > > > before initiating a Function Level Reset, and then ensure no invalidation > > > > requests being issued to a device when its ATS capability is disabled. > > > > > > Not really - what it says is that software should not expect to receive > > > invalidate completions from a function which is in the process of being > > > reset or powered off, and if software doesn't want to be confused by that > > > then it should take care to wait for completion or timeout of all > > > outstanding requests, and avoid issuing new requests, before initiating such > > > a reset or power transition. > > > > The commit message can be more precise, but I agree with the > > conclusion that the right direction for Linux is to disable and block > > ATS, instead of trying to ignore completion time out events, or trying > > to block page table mutations. Ie do what the implementation note > > says.. > > > > Maybe: > > > > PCIe permits a device to ignore ATS invalidation TLPs while it is > > processing FLR. This creates a problem visible to the OS where ATS > > invalidation commands will time out. For instance a SVA domain will > > have no coordination with a FLR event and can racily issue ATC > > invalidations into a resetting device. > > The sec 10.3.1 implementation note mentions FLR specifically, but it > seems like *any* kind of reset would be vulnerable, e.g., SBR, > external PERST# assert, etc? Yes. I forgot to put a question mark in the cover-letter, asking whether other reset routines would or not need the same trick. So, let's apply this to all the pci_reset_fn_methods.reset_fns? Thanks Nicolin